|
|
Please select the following issues that you believe EDA Tool Vendors should invest in based on your experience and design needs. :o
4 `8 l' ]( R G0 \. y t% o S/ K: ^, c
Add your comments to further explain how these issues are impacting your design process. And let's discuss these before 2008. ! b9 ^% V( I3 J3 ?
) {7 z% M4 t' g/ u, \
1.Time and schedule
( W+ x& z5 R& Y: S2.Parallel designs e.g. layout and design engineering working at the same time
9 L3 }! x7 C, z9 I' v0 E3.DRC/LVS/ANT verification
6 q; ~5 p: A7 ?# X4.DFT$ k9 R$ S& n. i2 k, d1 ^% b
5.Working in a multi user environment
; S+ @0 A" }7 l* j9 J' F6.Incorporating latest process node specifics (e.g. .65, .45 CMOS)
0 N) c( D5 A9 l5 P: S7.More than Moore technologies, such as high voltage design, high frequency design, high current design, high temperature design, multiple 0 E' f0 u: E" E9 A
technology support in a single design, Mems 6 v# q, g' L) P/ {, c" U2 S0 c( o$ e
8.Incorporating RF blocks into standard designs (RF SoC Design)
5 H5 A8 F# d' d$ K9.Dealing with low-power design constraints in an analog world/ i A8 {# ^1 B/ G! S8 T
10.Entering, tracking and verifying design intent between electrical and physical design
# T9 t- X9 ?! Q- p7 R11.Assessing parasitic sensitivities prior to full layout & J s8 v( s2 l, T+ _: D* X
12.Optimizing circuit construction at 65nm and below
( A- f1 ]% `/ V13.Techniques for design centering to achieve optimum performance / yield
0 ~7 Y- |2 x! R4 ~14.Designing up to to six-sigma yield margins+ R2 p( o: V' ]5 V
15.Other, please specify: |
|
IP卡
狗仔卡
發表於 2007-11-12 17:38:00
QQ好友和群
QQ空間
騰訊微博
騰訊朋友
收藏
分享
頂
踩
分享
提升卡
置頂卡
沉默卡
喧囂卡
變色卡
搶沙發
千斤頂
顯身卡