What Custom IC Design Challenges are you facing now?

jiming

Please select the following issues that you believe EDA Tool Vendors should invest in based on your experience and design needs. :o

Add your comments to further explain how these issues are impacting your design process. And let's discuss these before 2008.

1.Time and schedule
2 z4 [& {4 Y4 l" w' O2.Parallel designs e.g. layout and design engineering working at the same time
/ L+ j( E7 u! s9 m1 v) j3.DRC/LVS/ANT verification
# V  Q5 w2 l* ]* g! d+ q8 l* L$ F  s4.DFT
9 h% H5 {' {6 O6 m5.Working in a multi user environment
/ e1 R0 M0 {, V# q6.Incorporating latest process node specifics (e.g. .65, .45 CMOS)
1 I1 T, D# e1 g7.More than Moore technologies, such as high voltage design, high frequency design, high current design, high temperature design, multiple   
   technology support in a single design, Mems
, c( _. |% K8 ^6 z8 C6 ?0 ]# P0 a  |8.Incorporating RF blocks into standard designs (RF SoC Design)
: d4 [- ^+ S: e0 U  U9.Dealing with low-power design constraints in an analog world
, r6 l( k* j- @2 P10.Entering, tracking and verifying design intent between electrical and physical design
3 d+ ^0 S+ |0 y/ t3 w11.Assessing parasitic sensitivities prior to full layout
12.Optimizing circuit construction at 65nm and below
13.Techniques for design centering to achieve optimum performance / yield
14.Designing up to to six-sigma yield margins
4 H& \; I7 y8 m( w7 x  \' x  T15.Other, please specify: