Design of High-Voltage-Tolerant ESD Protection

semico_ljj

Design of High-Voltage-Tolerant ESD Protection
Circuit in Low-Voltage CMOS Processes

" X7 _7 w6 E' j9 T' Q! P* `Ming-Dou Ker, Fellow, IEEE, and Chang-Tzu Wang, Student Member, IEEE
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% s! N$ R- O+ ?/ Q, u/ e: RAbstract -- --
/ U$ p, W2 ^" Z$ L+ k     Two new electrostatic discharge (ESD) protection design by using only 1 × VDD low-voltage devices for mixedvoltage I/O buffer with 3 × VDD input tolerance are proposed.
! C3 o2 x4 A- }+ L: P+ qTwo different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD
protection designs have been successfully verified in two different 0.13-μm 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers. Index Terms—Electrostatic discharge (ESD), low-voltage CMOS, mixed-voltage I/O, substrate-triggered technique.

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yalon

柯老師的學術供獻.
令人敬服.
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收下囉.

D70s85

An interesting article. Thanks for sharing!! =)

sky987

柯老師的ESD技術 應該是全台灣最有名的
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希望給自己增長見識一番   科科

yihsinkaku

來研究一下HV 相關的ESD資料...希望能學點東西..謝謝您的分享

ecalfs

ESD really is a issue, specal for analog circuit.

chicken2221679

感謝分享!!!!正想學ESD相關知識~~~

samgu

來研究一下HV 相關的ESD資料...希望能學點東西..謝謝您的分享

starfish311

來研究一下HV 相關的ESD資料...希望能學點東西..謝謝您的分享

YoChin-hon@FB

  s# |- U+ W- O0 P# d+ u/ j3 ZThank u for sharing this material

傅偉豪@FB

看過後了解一些相關原理感謝

volleyfan326

Thx for ur sharing, it'll helpful to me.

weimaraner2136

感謝提供完整訊息幫助學習

justin7689

非常感謝您能提供ESD這個資訊 H2 }4 v1 i7 W2 H0 q' B 因為對於ESD還不是非常的了解 謝謝您的分享