請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
想要用軟體直接 run 到 IC Layout 產生 die photo,
& n" y( G6 h( T- F2 ^& y6 |要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
! `4 w* T# S) p, V2 Q1.
design compiler + Astro ?
) T: N% r* }8 e2 q/ A4 ]: I3 s
1 C5 |% \7 K( I7 l2.
synopsys IC compiler ?

$ Q& Z) [# q- v9 u. Y% j3.
cadnece virtuso ?

lee100

Synopsys R2G flow
1. rtl simulation by vcs
2. synthesis by design compiler ultra with dc/dct mode
+ g4 f& M* `. A7 W3. dft insertion by dft compiler
4. jtag insertion by bsd compiler
& |3 B3 x. o$ s, l( p5. ICG insertion by power compiler
, B% @% E5 b( L5 M6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
8. PnR by IC compiler
: j* O. H4 \6 Z% a9. post-layout SI analysis by prime time si
& L$ K. \8 I2 |, c8 R10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
clean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
2. Astro  from synopsys
: _' F" r5 @! _- v. S3 Y& n" o7 }3. FirstEncounter from Cadence
  m3 x, z$ |" d9 j) R5 Q/ n
: t& d6 c3 A$ J& N' z$ EAll with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好