請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
# [+ ~: ]( q; u- t2 ^- j+ ~想要用軟體直接 run 到 IC Layout 產生 die photo,
要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
. \( z$ p# d0 k4 Y1.
design compiler + Astro ?

2.
* n: t! `7 O0 M, o+ |: Ssynopsys IC compiler ?

3.
3 |; c9 h1 Z1 H0 I" i1 n5 j3 ?cadnece virtuso ?

lee100

Synopsys R2G flow
. n3 w& o/ A9 G; v# S' H1. rtl simulation by vcs
8 L; C( g$ I2 j$ k- J) V) n2. synthesis by design compiler ultra with dc/dct mode
" L  L7 G( S0 r3 K  h  c3. dft insertion by dft compiler
4. jtag insertion by bsd compiler
5. ICG insertion by power compiler
6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
8. PnR by IC compiler
  v1 Q5 @0 _; z6 }- T( M6 F9. post-layout SI analysis by prime time si
10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
clean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
2. Astro  from synopsys
) l$ G* h! O0 q& X% O3. FirstEncounter from Cadence
) q& g/ N( I& v) `' b" g% P
All with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好