LVS問題 望大大指點

xjyy

使用LEdit90的LVS時，顯示This file is Binary.LVS can not perform iteration.無法進行對比，這是怎麼回事呀

m851055

是比對檔案中路徑的問題，若有需要詳細說明把netlist PO上來................

xjyy

原理圖
! R: Z0 M! ]5 H6 s% P* SPICE netlist written by S-Edit Win32 7.03
0 ^3 W6 O  C5 Z) F2 Z1 U5 Z* Written on May 27, 2009 at 16:57:24
0 u. X% _! l0 r$ D* Waveform probing commands
! ]( ]+ y  Q7 M5 ].probe
.options probefilename="G:\tanner\Nand2_1.dat"
8 m7 e" o, r4 _+ probesdbfile="G:\與非門2.sdb"
+ probetopmodule="Nand2"
* Main circuit: Nand2
M1 OUT A N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 Gnd B N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
) Z5 W- p7 k7 J1 oM3 OUT A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
. \$ j+ v" V, ?9 H6 C. {% tM4 OUT B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
1 o" ^; P: s( F* b) U* b* End of main circuit: Nand2

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版圖
* Circuit Extracted by Tanner Research's L-Edit Version 9.00 / Extract Version 9.00 ;
2 O, ?9 ^. Q* Q4 R* TDB File:  G:\tanner\Nand2.tdb
9 ]+ W; ]+ \. b6 V3 {; D* Cell:  Nand2        Version 1.07
4 s  `. z2 Z/ @$ K1 C) Q* Extract Definition File:  G:\lights.ext
* Extract Date and Time:  05/25/2009 - 15:05
9 J% R' C  u' v7 z* Warning:  Layers with Unassigned AREA Capacitance.
& f1 k% H6 l# U& w*   <N Well Resistor ID>
*   <Poly Resistor ID>
" H$ u6 X' ?3 i  H0 j" P2 B3 _*   <Poly2 Resistor ID>
*   <N Diff Resistor ID>
: A/ M! Z. r  k5 x*   <P Diff Resistor ID>
8 d# A% D# `8 F  O: O# _6 U*   <P Base Resistor ID>
0 F0 ^- W7 Z9 y( W8 J3 r* Warning:  Layers with Unassigned FRINGE Capacitance.
*   <N Well Resistor ID>
/ V& {) ~6 L5 y2 C! S*   <Poly Resistor ID>
*   <Poly2 Resistor ID>
*   <N Diff Resistor ID>
*   <P Diff Resistor ID>
; D& e; ^. N9 V" V3 G6 w0 z*   <P Base Resistor ID>
9 s2 e% Q1 N! ~+ b*   <Pad Comment>
*   <Poly1-Poly2 Capacitor ID>
* Warning:  Layers with Zero Resistance.
*   <NMOS Capacitor ID>
2 |% `' I, {% w; l*   <PMOS Capacitor ID>
*   <Pad Comment>
8 j, h: E* H% [& h8 K: N*   <Poly1-Poly2 Capacitor ID>

* NODE NAME ALIASES
*       1 = B (12,-14)
* B' R# C$ @" L0 t! R/ [- u9 `0 H*       2 = A (-16,-18)
0 r: K% J/ Q& {0 [*       3 = OUT (-2,-21)
*       4 = GND (-30,-35)
0 e7 E1 r/ Q$ l- P1 V5 G*       5 = Vdd (-32,14)
M1 Vdd B OUT Vdd PMOS L=2u W=6u
* M1 DRAIN GATE SOURCE BULK (3 -3 5 3)
M2 OUT A Vdd Vdd PMOS L=2u W=6u
* M2 DRAIN GATE SOURCE BULK (-5 -3 -3 3)
) N7 }3 h/ X: o& Z; YM3 OUT B 6 GND NMOS L=2u W=6u
* M3 DRAIN GATE SOURCE BULK (3 -31 5 -25)
M4 6 A GND GND NMOS L=2u W=6u
* M4 DRAIN GATE SOURCE BULK (-5 -31 -3 -25)
* Total Nodes: 6
* Total Elements: 4
* Total Number of Shorted Elements not written to the SPICE file: 0
! x9 U& h& o# R( m* Extract Elapsed Time: 0 seconds
.END

m851055

與非門2 files name改為英文名稱.......................

xjyy

我宅了一周 沒想到栽在路徑上  萬分感謝 ！！！！！！！！！！