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//some example
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// define variable
5 q( |0 l$ m/ O; F; AVARIABLE RVM1 0.077 // Metal-1 resistor
! p$ `0 G& w7 V7 `0 sVARIABLE RVM2 0.055 // Metal-2 resistor; i4 w- j+ Q- \% f& f- g# R0 K( I
VARIABLE RVM3 0.055 // Metal-3 resistor
( Y. D+ |" \( C
0 H4 H1 N3 O# c% |# C6 ]: y3 t// lvs option
6 c$ ~, P$ y9 C$ n3 @7 w( DLVS SPICE PREFER PINS YES* I7 u6 B0 @6 F# p& Q
LVS ABORT ON SUPPLY ERROR NO
6 M5 `. C2 e0 `$ I# |LVS ALL CAPACITOR PINS SWAPPABLE YES1 y4 @* X1 @: D
LVS RECOGNIZE GATES NONE
" r5 y1 x! F4 s; Y7 Z( K4 c# e" t; C! SLVS IGNORE PORTS NO9 N/ Z l% B3 h# k# X/ Z! {* w5 j: [( e
LVS CHECK PORT NAMES YES6 l& p8 u$ L& F# |: R5 P1 {
LVS REDUCE PARALLEL BIPOLAR YES1 U9 Q! q3 t" z7 g( f& B
LVS REDUCE PARALLEL MOS YES, L* B* r# x$ l# [8 h; r
LVS REDUCE PARALLEL DIODES YES
' k, A/ ~/ |, J* D9 nLVS REDUCE PARALLEL CAPACITORS YES
6 j9 L* i) H1 O1 r A# qLVS REDUCE PARALLEL RESISTORS YES
! ?9 V2 H, U8 [2 _5 cLVS REDUCE SERIES RESISTORS YES //Smashes series resistors
) L: g; x: ]5 t& k' E5 t6 jLVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors) Y/ u% \4 D! J; i
LVS REDUCE SPLIT GATES NO //Smashes MOS split-gates.2 @. E: z0 g% J
//LVS FILTER UNUSED OPTION B D E O
. [ ^0 L8 x) r+ w' _+ rLVS FILTER UNUSED OPTION AB RC RE RG p. E/ _3 |/ a& t
LVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL
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0 n$ U) F4 k& A3 R& |9 _6 L5 G( G// layer definition
6 t, e2 A5 B) m G' H. H& p, |LAYER DNW 1 // DNW -- Deep N-Well
# B6 m/ X4 R4 U. ALAYER NTN 11 // Native Device Blocked Implant& ]7 ~+ J% C8 y9 D5 L4 A
LAYER NWELL 3 // NW -- N-Well. T X% T9 b) E: G8 l3 F
LAYER OD 8 6 7 // OD -- Thin Oxide
% p9 O- r) E1 X2 O% l( v' ?4 U/ L
// layer operation7 K0 U; ^+ B! m/ }- Z7 Q( g
rpolywo1 = POLYG AND RHDMY , `, I+ B* n% j
rpolywo2 = rpolywo1 AND RPO ; ~1 D! V- E9 U" Q) z: S( T: V2 { O
diff = OD NOT RODMY
" X. z- }7 j- W2 U( y* vrp1 = RPDMY NOT INTERACT diff
: U4 M2 j# v( q5 C$ ^p1rdum = rp1 INTERACT POLYG
* A; V4 p: e" d+ U; e, I6 T% Z' n5 a$ G
// connect statement1 z7 F4 r" J: S8 E8 j
CONNECT metal1 c2poly BY pl2co
0 v, u; w& u. J JCONNECT metal1 tndiff BY pl1co
" O# i0 L9 u/ _5 \+ z& uCONNECT metal1 poly BY pl1co
; v5 H! \; u+ O1 K9 HCONNECT metal1 tpdiff BY pl1co
/ l: M- \; W. m! B5 OCONNECT metal2 metal1 BY VIA1
3 K$ G$ n8 m2 h G4 P' ?7 }CONNECT metal3 metal2 BY VIA2
N9 q, _$ Q0 @. Q7 d7 pCONNECT metal4 metal3 BY VIA3
5 S4 N5 h1 m9 s0 t0 c- U- aCONNECT metal5 metal4 BY VIA46 P: [! P! w2 n
CONNECT metal6 metal5 BY VIA5
( [4 t5 c& H9 x QCONNECT metal7 metal6 BY VIA6! G b9 S6 b8 Q; a/ X
CONNECT metal8 metal7 BY VIA7
8 Q8 }4 K- ]5 f( ~/ @CONNECT metal8 CTM_M7 BY CV7
+ S. E" K0 ^) ^
}& U$ T, ?8 v. E// device definition" b4 W9 a @% r' q# W8 q- M
DEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [4 ?6 x s Z, Q. B& j+ x4 H' }* u
property W,L( y' \3 R' u% ~, Y. N5 D2 b& _) {
W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 2; T. i* g8 o- G, T3 m1 [( i. l
L=area(nmos) / W
. F4 j2 Y% w# U. d8 s]. f8 j5 C3 A+ M( B6 p
! o* X" |; v" c/ N// trace property" ^* E5 A( Y1 e# K' f4 B
TRACE PROPERTY MN(nmos) L L 0
; m7 h5 c+ k! @. S8 g8 kTRACE PROPERTY MN(nmos) W W 0 |
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