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//some example
6 O; `; @& b' c" h' y* y. M3 \; L1 H! i8 k; [: m4 [' `
// define variable
! I( `4 f E) k1 N0 aVARIABLE RVM1 0.077 // Metal-1 resistor
7 _9 g: b& B8 {- EVARIABLE RVM2 0.055 // Metal-2 resistor% c& {( a' H0 y: O& u s
VARIABLE RVM3 0.055 // Metal-3 resistor4 Q3 Z$ v% }. ^4 K! F ~/ s
. M2 m2 L* F: h4 l% }; Y
// lvs option& D/ f* T) T H& d l
LVS SPICE PREFER PINS YES
. v- C* ?- X! RLVS ABORT ON SUPPLY ERROR NO
\- G) u: C2 h# }% b# `( zLVS ALL CAPACITOR PINS SWAPPABLE YES
& S9 k7 Z4 |8 i; x% MLVS RECOGNIZE GATES NONE
" l% @% x% @0 F5 cLVS IGNORE PORTS NO: Z) K$ f4 O' v
LVS CHECK PORT NAMES YES
' ^9 J- U h( f3 F# gLVS REDUCE PARALLEL BIPOLAR YES( w2 J8 C1 M: l n0 w# U
LVS REDUCE PARALLEL MOS YES
0 D! J3 E. m/ v7 zLVS REDUCE PARALLEL DIODES YES
& }# M, L, @; \LVS REDUCE PARALLEL CAPACITORS YES
/ I1 z+ Y1 l7 X; F7 ]LVS REDUCE PARALLEL RESISTORS YES
v% H& x$ u u2 p7 U% eLVS REDUCE SERIES RESISTORS YES //Smashes series resistors
9 N5 @1 H, m7 r) j$ v0 QLVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors
4 ?3 V# K/ A7 ?9 H. D! gLVS REDUCE SPLIT GATES NO //Smashes MOS split-gates., I) e! ] C X6 t$ f- O
//LVS FILTER UNUSED OPTION B D E O
6 _6 m: ^! r: M: x1 ULVS FILTER UNUSED OPTION AB RC RE RG: Q% J) ?" \$ C, h
LVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL
! j3 Y0 G8 {4 W2 T5 K4 _3 r' t1 d, J4 l$ H
// layer definition
! e" P' n9 v& O) y! F$ b! FLAYER DNW 1 // DNW -- Deep N-Well% ]* K$ C3 X7 \+ y+ K' H0 W7 X- U$ s
LAYER NTN 11 // Native Device Blocked Implant+ [3 P2 k3 z; P9 s1 n
LAYER NWELL 3 // NW -- N-Well
# v& K/ K: s$ T3 ]. rLAYER OD 8 6 7 // OD -- Thin Oxide
6 K0 D8 p, u+ S2 l+ L
4 ?# T7 I5 \/ i" ^$ l, l// layer operation
7 O" \- a+ h1 n6 h5 Q% Jrpolywo1 = POLYG AND RHDMY V1 s: S- t5 ~6 C/ _4 c
rpolywo2 = rpolywo1 AND RPO
. O) F' o4 ]' M: w2 ldiff = OD NOT RODMY
* ^1 d, O, X- trp1 = RPDMY NOT INTERACT diff
9 N2 G- T( @5 \" i' u+ C! dp1rdum = rp1 INTERACT POLYG
9 ?' F$ Q% w" M! I$ m" e
7 q1 N* A5 ?5 Q6 O2 L6 g- E// connect statement
+ W' x; c- B9 a( u. c; zCONNECT metal1 c2poly BY pl2co
2 U) v& p a. gCONNECT metal1 tndiff BY pl1co
" @1 t: K+ {# ^, h( ?1 tCONNECT metal1 poly BY pl1co: J" \1 X% g4 g
CONNECT metal1 tpdiff BY pl1co( q& a2 ]7 M$ @" s- ]3 w
CONNECT metal2 metal1 BY VIA1
/ ^1 F% H# h3 W9 B0 UCONNECT metal3 metal2 BY VIA2
3 i. R {) W* Z7 t6 d4 aCONNECT metal4 metal3 BY VIA3& q! J. e% H8 m% M/ t
CONNECT metal5 metal4 BY VIA4& Z/ J$ `; z; V; i! ?! I j/ |! I
CONNECT metal6 metal5 BY VIA59 Z" y1 \( x& c: U( G
CONNECT metal7 metal6 BY VIA64 A t3 @% \! q2 ]; k; B
CONNECT metal8 metal7 BY VIA7# e# W2 M. t K- A0 d1 w. r `
CONNECT metal8 CTM_M7 BY CV7% y- v, k& i# z& \( w
8 h0 V' | @, L+ [4 L
// device definition# e1 m2 B& ^. O& ~
DEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [1 t3 `! W$ @2 i- R* C
property W,L5 [- y7 d, h( r0 T
W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 2
) _9 o- u# o# k7 |: x6 W L=area(nmos) / W
! P/ h( E% F( E+ B]
q3 ^' W. g% u% }/ \+ C
8 e6 Q" S1 W4 ^& R% r// trace property9 Z/ b+ R/ G" B0 G/ m, b; ~5 f7 O5 e
TRACE PROPERTY MN(nmos) L L 0
) ^7 U+ v- {# }6 u4 q g eTRACE PROPERTY MN(nmos) W W 0 |
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