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LOAD SDC FILE時
/ }- f6 r+ ~# xAstro 訊息
4 W# x7 K" d2 x2 [---------------------------------------------------------------------------
2 |1 K3 F" }! k6 i$ P. n* qInfo: starting Tcl processing& W' D. Z- C, Q
Info: building design object name tables
. u/ S) n" M" ZWarning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)
# \/ {0 Q9 i9 bWarning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
q! }/ b- W* l A0 ^# o' V+ \7 v- S$ j5 G6 h* M
----------------------------------------------------------------------------" w/ t# ?0 C' Y0 e
SDC FILE4 E2 W2 g0 n6 i, e
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set_multicycle_path 9 -through [list [get_pins \
% M, Y1 p6 Z& p/ Z- o) o3 {1 O3 P{TOP/test/mul/A[26]}] [get_pins \
( h8 C3 A5 X5 I# |5 ~{TOP/test/mul/A[25]}] [get_pins \
% |4 q l$ l9 j+ I" O. q* }( l o
3 L' ]) f' L* ^8 ~- }
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' E4 Z* _* q) [% Z& w/ uVerilog File- q7 y+ }- w$ ~; N7 \
$ u5 G" S" s7 _' R
uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(: B! Y+ B5 l8 H. B4 l
icwAeYfNum[18:0]), .C(ae_avg) ); |
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