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LOAD SDC FILE時
% G9 n: S) D+ R/ Q. |0 C: GAstro 訊息
5 c8 K/ X" T5 j; P: h8 t9 ~: s---------------------------------------------------------------------------
2 r) J9 K4 j! e! A wInfo: starting Tcl processing# ~1 p8 N. w: W3 p( G
Info: building design object name tables
$ y* h( n- F" KWarning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)! l/ N o2 [" O& ~6 k
Warning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
6 [# J# ?( o, d: E. c
' G) W1 l3 u1 D4 h2 C0 J7 `' i----------------------------------------------------------------------------1 \" y" m$ j/ Y" x! i6 H
SDC FILE
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set_multicycle_path 9 -through [list [get_pins \5 e' _& l6 N5 a* H$ U
{TOP/test/mul/A[26]}] [get_pins \1 X- f( y* h; M+ T& D) ?
{TOP/test/mul/A[25]}] [get_pins \ O- D% W2 c. R3 A1 x1 `9 Y0 _
0 }3 n! ?1 |. A/ i
8 ?9 n6 A+ Q6 {' d/ E' a* E-----------------------------------------------------------------------------
/ M4 _' U& @. ~) f& LVerilog File8 A' S5 V2 e- t
& L5 X2 Q- k$ B' q2 h
uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(
! ? B+ m3 m8 H5 [ icwAeYfNum[18:0]), .C(ae_avg) ); |
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