11/19-20 Semiconductor Manufacturing Forum 2009

chip123 · 發表於 2009-10-21 17:58:10

由台灣半導體產業協會主辦之「2009半導體製造技術論壇Semiconductor Manufacturing Forum 2009」將於11/19-20於新竹交通大學舉行，會中邀請關於Thin Film、Asembly, Packaging & Testing、Diffusion、Design, Reliability & Testing、Litho與Etching等專家對未來趨勢與新技術進行專題演講，是半導體專業人士不可錯過的一場盛會，即日起開始報名，歡迎各界踴躍參加。

2009/11/19-20 National Chiao Tung University Library International Conference Hall
交通大學浩然國際會議廳

Agenda 議程
Session 1: Thin Film (11/19 13:20-16:20)

' l: }/ x4 H9 w L+ r( R$ _	Topic	Speaker
13:20-14:00+ a( m5 H* Z$ S( e) R4 d4 o- w	Engineering Slurry for Copper Chemical Mechanical Polishing - Y; L4 K/ g5 [* t) a	Dr. Song-Yuan Chang / ( \|. V! \1 ]1 `7 `CTO& senior VP, UWiZ i: e, c9 H6 \- f( @6 V# y: sTechnology
14:00-14:404 T( e7 ?7 x- P	Tailoring CMP Consumable Sets To Meet the Increasing Demands Of IC Device Manufacturing For Advanced Nodes	Dr. Fred Sun / Cabot " Q& } T# j7 B% M: {% F0 I
14:40-15:001 r% V0 g3 `8 t2 q/ @	Break : U, @( R) h7 {0 j t4 j& _	. ^9 w3 Y3 E* r+ z1 K* b, a/ i
15:00-15:40 1 G" ~! j) T0 }% F/ P6 P% k3 y1 @4 ~	? ' Z# R& e' R8 o3 b+ h	Apllied Materials) Y& @& n% s& R
15:40-16:20# ]* L5 l- e T$ t* _	CMP Fundamentals and Implications for Consumables Design % A8 Y* `6 C' G0 B) B2 G	Ms. Kate Kao/ Marketing Manager Dow chemical3 _9 D" w# L/ B w$ t, Y7 o

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chip123 · 發表於 2009-10-21 17:59:25

Session 2: Assembly, Packaging & Testing (11/19 13:20-16:20)

& f+ B, S; R: ?+ r6 C	Topic $ n& \|* E6 h _. D! f/ w7 w2 r	Speaker! f" i) _4 R. G7 m' \|7 w' B
13:20-14:00$ P) D: K( r; }	Sip Assembly technology? % E- E( v4 ]& [' ?	Dr. KC Yee/ VP, ASE- x/ o$ y0 Z7 V' v6 A6 l
14:00-14:40: I- W/ C0 T3 c L1 r7 ~3 J	Assembly trend from perspective, v4 L6 j, F6 {( F	邱世冠資深經理/矽品 6 m9 L( ?0 Q3 ~, u前瞻科技中心# j5 J6 H' f @1 ~* T
14:40-15:008 \ z7 H- `" N) {5 S# L. o	Break, Y6 v( h" f$ C7 X1 ] i s	$ \$ I! ^6 O2 r) f3 G3 g. k4 s
15:00-15:40 & T! i F6 K( F4 V) T	The Paradise of Cost-Effective Wafer Probing Technology 3 o L! D( L# U+ O* Q	Dr. CCNi / Associate Director , KYEC 1 y5 ]2 n# F4 G( n' K
15:40-16:207 c+ F/ K1 N9 I4 s	RF SOC /Sip?! j1 b% A7 p( P8 d2 \|/ V+ x9 v, d	Verigy: {" {5 K/ j) Z- D; I" J2 j4 s

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chip123 · 發表於 2009-10-21 17:59:56

Session 3: Design, Reliability & Testing

* I) L2 T6 h# Q6 \- h1 W! [. F6 t	Topic( {* g5 l+ `! r l1 v/ [	Speaker ; L& `+ X) ?8 H7 ?2 U; N/ j7 B! c
9:00-9:400 a8 N: Y) N: V8 A1 _& V% m	Design Trend? " k1 W% _" D% K& F1 A	Marketing VP, Dr. Chiang Alchip $ O# s3 R/ @2 o g$ W+ u: y
9:40-10:20! w& J( V# _9 d2 j, P- U3 j	Charged-Device-Model (CDM) ESD Protection in CMOS Integrated Circuits ( }/ m/ z0 L: a8 [	Prof. Ming-Dou Ker / I-Shou Universit 9 b* E; d4 U) T
10:20-10:40 4 O/ g c% Z' _" u3 [" p	Break 7 ]$ j0 X. M) K8 g+ I/ i" {	- y# r1 }; w; G
10:40-11:20 0 F+ U" x$ V% Y# H6 c D/ t	Parametric Test Challenges of the Next Process Frontier 3 j# ]6 j2 r0 i+ p/ M% _	Ms. Flory Tsai / agilent * A/ w3 K3 V1 M e( O8 I
11:20-12:00/ Y, r9 h, D" y' \|% X+ D	Recent Development Work and Trend for Semiconductor Device Characterization & ~ r3 ?5 \- Y8 ` X. W: p- o& i	AL Feng / 專案經理 / Keithley Taiwan ' {3 [' V* L t8 e$ y9 e2 l

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chip123 · 發表於 2009-10-21 18:01:32

Session 4: Diffusion

/ W" o1 Q( b8 F! S	Topic 6 O. S8 z: O- E; R	Speaker 0 Y# y" @* \ E4 g4 Q) ]
9:00-9:40- W7 J" J( M( `- o* o6 M8 d* g	Surface Preparation process control requirement to support CMOS scaling into 22nm & q3 R1 f. E% v4 g* ~1 ]	Dr. Scott Becker/ Vice President, FSI2 ^" Q0 N' V N$ G8 q* b+ \|0 @
9:40-10:209 C% A4 [5 H; f& O/ t	Wafer techincal roadmap and application for advanced or special proces% f7 l. Q; k/ _! Z8 p	MEMC 3 e G4 u+ T) f5 j, k/ j' \|3 Y
10:20-10:402 X. I* l* g0 j2 X3 \! V% L) _	Break 6 n+ v! Q7 R( U$ X! b b	9 v& d4 ~. t- H( g) K" v0 y/ i
10:40-11:206 o: V' `& v i) K! g	# J6 n0 w o$ @- h. C	9 V% e8 s' B4 J6 Q7 ^

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chip123 · 發表於 2009-10-21 18:02:03

Session 5: Litho

( [# \% e* @- J5 c7 j7 b	Topic; F/ r0 d1 Z8 v% `* G m	Speaker 4 ^4 Z# j5 T2 ~
13:20-14:00 ; U* Q. _. J9 A$ s# j, T	Photomask technology for 32/22nm and beyond p. P. Y, Q+ M2 ?$ ^	Dr. Hiroaki Morimoto/Senior General Manager,& i% b( N5 t9 r/ I% { Toppan Printing! l9 \|% _: e& m4 P- K
14:00-14:40 % h7 r% n# R+ R3 i0 ]* l; R	3 I, I# v$ m, k9 n Implant Resists for Advanced Node Applications/ w! Z& h7 `6 d v' V- y; b	Mr. Yoshiro Yamamoto/ ! `* J) }- O7 p9 \" J DUV RD mamager, DOW8 j) a- a* j5 G 6 z! `- t8 K: w8 M3 m4 f( v4 Y d Semiconductor Technology & y" g8 ^# H& X
14:40-15:00" l& a8 \% Z" l. P	Break2 N1 a2 i: O! {; z3 b, T! p	! R! y& V v1 O1 G4 s
15:00-15:40: Q5 p6 ~1 [$ m [; S	State-Of-The-Art Development of BARC Material $ h, R2 U5 }# ]3 r0 Y; A	Brewer Science* u9 P3 X" \|* {7 G, s! t& R; \
15:40-16:20! ]$ o9 a! [+ X3 G	The Future Trend for Next Generation Lithography 6 C2 {) p7 F5 O' S5 I	ASML + t( u1 G/ v# c' u1 A. U9 `
16:20-17:00/ q. I1 u: N* }0 x: z4 S T1 L	Future Trend of Track Technology 0 E' [3 D2 L( n& }' Z	TEL 5 _8 y1 c2 R$ G; e; \- S; U4 d

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chip123 · 發表於 2009-10-21 18:02:34

Session 6: Etching

! p0 h& C1 a/ E' g2 S3 G' W	Topic 7 ?. o9 g- S3 z% R0 F# S( f, x' c) s	Speaker( p3 o; U1 h$ `5 Z1 S$ V' }
13:20-14:00 * o9 k# G `. y3 h2 U+ D- [	The Advantages of real-time wet process monitoring by multi-channel, in-line NIR analyzer " f3 R0 \* o& j! K. f: @	Mr. Shay Tina / CI Semi , Director of Sales - l4 e9 A$ V' k3 @ B& r0 ?
14:00-14:40( B6 U4 @* z& G& Q& x' a	Green Chemistry for current technology and beyond! j0 y1 C& g: O: ~% A" K$ z	Mr. Elvis Sheen / Mallinckrodt Baker, Senior Manager3 k" H0 ~$ E+ d# P% p8 H
14:40-15:00 ( J. ]* o( }. r$ ]. D4 Y/ P; K	Break! m- e- [4 O) }	# i! G/ i2 \& X- u
15:00-15:40. M* T1 c- \|9 W( v	Post-etch residue removal for advanced copper low-k device 3 H, P- W. m I9 p3 `( L& J* c	Dr. Hisashi Takeda / EKC Technology, DuPont 6 \ @# M9 u- J- q0 c1 v; n8 W
15:40-16:20* N% _4 E3 r% C6 c9 T. Q	Edge Die Yield Improvement with Immersion Lithography Defectivity Control by Bevel Etch Clean g- Y4 n4 t0 N	Lam Research, X& x/ t+ U( B
16:20-17:00 2 d" w! ]9 p; l- t7 t	Improved Control of Through-Silicon Via Profiles for Advanced Packaging Applications7 o5 w1 v8 v1 }/ `6 V	Surface Technology Systems + x( }. Y6 ~ K# U+ @

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