11/19-20 Semiconductor Manufacturing Forum 2009

chip123 · 發表於 2009-10-21 17:58:10

由台灣半導體產業協會主辦之「2009半導體製造技術論壇Semiconductor Manufacturing Forum 2009」將於11/19-20於新竹交通大學舉行，會中邀請關於Thin Film、Asembly, Packaging & Testing、Diffusion、Design, Reliability & Testing、Litho與Etching等專家對未來趨勢與新技術進行專題演講，是半導體專業人士不可錯過的一場盛會，即日起開始報名，歡迎各界踴躍參加。

2009/11/19-20 National Chiao Tung University Library International Conference Hall
交通大學浩然國際會議廳

Agenda 議程
Session 1: Thin Film (11/19 13:20-16:20)

0 l/ i8 Q5 e9 P	Topic	Speaker
13:20-14:00/ }& t6 P/ D7 }: v	Engineering Slurry for Copper Chemical Mechanical Polishing ( J6 K3 c; M4 {3 X4 N# x2 a	Dr. Song-Yuan Chang / , l' s3 D" L7 d; E4 {8 A& s' mCTO& senior VP, UWiZ # q5 Y2 U9 M! Z1 iTechnology
14:00-14:40	Tailoring CMP Consumable Sets To Meet the Increasing Demands Of IC Device Manufacturing For Advanced Nodes	Dr. Fred Sun / Cabot % a1 z4 o9 y- v$ h
14:40-15:00' D8 a8 o# K g, F# @: w* _/ H	Break 0 y8 q1 _7 G7 F) g	2 {$ M7 I& @% C: C* K! ?
15:00-15:40$ a; o9 c6 B0 ~4 r1 S$ O	?" K! m$ C% x! G. e* D, d1 t	Apllied Materials * w7 z4 O" W6 ?4 ?; ^7 c7 R
15:40-16:20 7 f) q M' {* I! W; B1 {0 _$ u	CMP Fundamentals and Implications for Consumables Design 8 I) ]) y; D( m4 c4 O4 m	Ms. Kate Kao/ Marketing Manager Dow chemical / p( ?, p8 \| ^. y( U

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chip123 · 發表於 2009-10-21 17:59:25

Session 2: Assembly, Packaging & Testing (11/19 13:20-16:20)

d- g* H! u; G1 t0 A! z( p1 S5 Q1 d5 x	Topic : v. M R/ B, B! n0 v	Speaker ' I% j. L; K8 L9 I3 w
13:20-14:00* P! \|) t/ i+ n, \$ R$ J	Sip Assembly technology? " M7 l6 V3 E3 H8 r$ O! W	Dr. KC Yee/ VP, ASE ( u; P$ _4 r: @( B$ H: J' u
14:00-14:40 : l$ K+ X& j, B! g' B* b	Assembly trend from perspective& P$ T- c( W' N" U. \|- Y	邱世冠資深經理/矽品 6 y" g- E+ F, K6 L; A前瞻科技中心& D9 v8 i% _4 ~2 `. H
14:40-15:000 n) t7 S: M6 v* M4 A2 ~	Break / ?$ a- f, M$ c4 q	' }2 ~( F4 Z( l p8 A0 o" B! C4 q; k
15:00-15:40+ P# V. ^ T* S: P6 w	The Paradise of Cost-Effective Wafer Probing Technology . k3 o4 p s( L0 \|7 D7 M	Dr. CCNi / Associate Director , KYEC ! a( Y; `7 t' u$ J% r' w4 d) Q
15:40-16:20 # ]/ ?& F8 j4 \% y8 f9 l9 }6 ?7 q+ Y	RF SOC /Sip?/ [" S6 @: S5 U7 r" i& o) I	Verigy ) f' R4 T5 w: V$ A

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chip123 · 發表於 2009-10-21 17:59:56

Session 3: Design, Reliability & Testing

8 _4 M! {) i" j k0 T# S3 o: ?. \|4 o	Topic 9 ~5 n" F& y, ]% L6 ~' z- t	Speaker 3 X& b" ~6 }! h/ E: y
9:00-9:40 0 w1 w! h1 s* t# `$ o	Design Trend?2 U* G/ J5 V2 ^& E9 ~% E: L	Marketing VP, Dr. Chiang Alchip7 y4 u! Y1 p1 H
9:40-10:20' }7 E1 k2 \5 n7 M; ~# ^* G% L. z# {	Charged-Device-Model (CDM) ESD Protection in CMOS Integrated Circuits ; L# l) Z7 C9 k& \|: j	Prof. Ming-Dou Ker / I-Shou Universit ; n5 `, T, B) {- q3 t
10:20-10:409 M: v2 V4 y7 e) C	Break 3 `; r! X/ X: ] D" S; \|" J0 }	p# n# K: u# U8 m* w8 O6 ~" `
10:40-11:20% e, c2 o% u- [ h. N, Q x) B	Parametric Test Challenges of the Next Process Frontier 5 y% s; \( H3 {	Ms. Flory Tsai / agilent # a' V+ {! G, E6 M
11:20-12:00 + e2 Q8 \|1 y' t# @. S	Recent Development Work and Trend for Semiconductor Device Characterization 7 q+ [: I \|: r- N$ D' Q	AL Feng / 專案經理 / Keithley Taiwan : H2 x/ N) `9 t0 E* W% M

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chip123 · 發表於 2009-10-21 18:01:32

Session 4: Diffusion

: r6 q ~* @4 h- d/ ~3 f	Topic . \" R9 Q4 Y+ e9 o+ {	Speaker 9 w( U- J& e1 f# Y$ ^
9:00-9:40 ! s# d8 K% z7 o$ a* d8 A/ k	Surface Preparation process control requirement to support CMOS scaling into 22nm 3 _9 X- } X( N( B& Q	Dr. Scott Becker/ Vice President, FSI . A: a$ v4 t U
9:40-10:20; p2 x9 ? ~% h; J* T	Wafer techincal roadmap and application for advanced or special proces2 ?& o' N/ u3 Y% e: S1 G	MEMC ' U8 h5 J8 r( {, \% f! n% B
10:20-10:40 3 v0 ~1 ?1 E" x/ \# C8 G! M	Break8 y# a+ E: ~; W7 K6 u	4 b& i. C3 A; s( ~6 v5 F; Y5 q
10:40-11:20 4 \|* T3 v0 H( L& e	5 J& q' P; u, c! ?3 s/ _	, W. \: E: c7 O! P* }$ ?) I

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chip123 · 發表於 2009-10-21 18:02:03

Session 5: Litho

0 i/ q. f! G6 m% P( \	Topic & h% m6 M/ b' W+ {	Speaker 2 ?9 n3 r* i2 ?, m* \|( f9 o& n
13:20-14:00 : D, C0 l. s# `	Photomask technology for 32/22nm and beyond " Y8 r) I9 u$ t	Dr. Hiroaki Morimoto/Senior General Manager,0 ]# T4 e# E2 ~ p3 d Toppan Printing % d2 q( I) i0 @1 Z) X6 L+ M0 b- ~
14:00-14:40 7 h3 q% D+ Z* r) \	0 a3 K" w: o1 U* u2 ^, gImplant Resists for Advanced Node Applications ' ?' T w) C8 Z* e5 @0 _2 T/ m	Mr. Yoshiro Yamamoto/ ; h7 g+ ]6 }2 f1 W9 F, B) \|) f DUV RD mamager, DOW ) @* ?$ J* k1 `3 l7 k2 E * ?3 I v7 ]: b* [' B' pSemiconductor Technology 3 g6 E2 \|! i9 d% c$ D
14:40-15:00 ' X# P+ T U8 ~6 v7 o. T x	Break + T6 Y' l i, a- G	7 x* ~2 f; G% J4 P. c
15:00-15:40 B' g, Z: b( d. X	State-Of-The-Art Development of BARC Material ^1 [7 j' o# [+ ^6 l8 o2 r	Brewer Science / i% X' x. ?; Z4 f1 d
15:40-16:20 2 o& @) n: D3 e; E. x	The Future Trend for Next Generation Lithography ' V& k$ G* u9 S) C0 x	ASML" m Q* C* ]: d$ V/ Y% p# h4 F
16:20-17:00# N# y3 ]. d6 a+ Q) q# t$ H	Future Trend of Track Technology / v7 s# e0 P) ~( b	TEL " Z/ @9 D' z! C6 W H" [2 M* U9 {

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chip123 · 發表於 2009-10-21 18:02:34

Session 6: Etching

/ B# ?$ x* d8 z4 L	Topic# e- V5 \|& g. O3 s [: N	Speaker 7 v* O7 Y o0 g' Y
13:20-14:00, ]* f6 w, O+ k1 z4 v% t	The Advantages of real-time wet process monitoring by multi-channel, in-line NIR analyzer ) b5 c3 T9 e/ i8 F+ `) e# B	Mr. Shay Tina / CI Semi , Director of Sales 6 y+ a$ o) C) d/ y' @% ^
14:00-14:40- C0 `5 Z! h2 q Z' A; e	Green Chemistry for current technology and beyond) D2 R3 v- \; W# e5 d5 {	Mr. Elvis Sheen / Mallinckrodt Baker, Senior Manager & ^( {) {3 o8 \9 p, j7 D4 @9 ]7 @- ?
14:40-15:00 6 H# r% ^3 v& ^3 F	Break ' N) {( O! F- F! V& B8 e1 E6 }	' R: c O. k! ?
15:00-15:40; e9 T. h; `8 K7 e/ H	Post-etch residue removal for advanced copper low-k device * E4 f2 r! }5 ^	Dr. Hisashi Takeda / EKC Technology, DuPont 7 y0 Z- u7 f) g" b% v
15:40-16:20 8 R4 M7 K7 ?; [. H	Edge Die Yield Improvement with Immersion Lithography Defectivity Control by Bevel Etch Clean& B6 y( H1 q: K$ M8 J1 Q+ n	Lam Research / I* Q4 g# Z+ r! _! G
16:20-17:00 9 C& J9 b1 ]9 k* J" H2 v1 ^' A3 R	Improved Control of Through-Silicon Via Profiles for Advanced Packaging Applications) P4 {, X, P7 p9 r6 Z9 c	Surface Technology Systems: W" [8 W0 r& {4 w+ @

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