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| SH77722 (SH-NaviJ2) Specifications
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Type name
* {1 O8 r! X2 o8 z) d T | R8A77722DA01BGV8 P3 O9 U2 Q9 N5 q
| R8A77722DA02BGV
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Power supply voltage
% V6 H- o& ~, A' z | 1.15 to 1.3 V (internal),
1 r8 V2 P( L$ e, B; [! t X" V+ g; p3.3 V and 1.8 V (external)* G5 k; C$ o' p9 ~* y
| 1.2 to 1.35 V (internal), , ^' O1 g% a1 D6 |+ k4 [( K! ?- ?
3.3 V and 1.8 V (external)
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Maximum operating frequency; r% S) f" M$ d
| 336 MHz" g4 K: v6 f/ y
| 400 MHz7 S" k+ g5 G Y* h
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Processing performance- ?6 w) A7 r9 O+ }
| 600MIPS, 2.3GFLOPS
2 u$ z& i6 x8 |" O3 [ | 720MIPS, 2.8GFLOPS$ X: y3 {- ~ h7 V
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CPU core
5 o- I8 j0 ]7 A" m! j" k | SH-4A core& r2 m5 n* x7 H7 P6 X
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On-chip RAM w1 e6 [ k; N" X) p* ]
| ILRAM: 16 Kbytes
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Cache memory# ~3 l2 J, q1 E4 J/ G9 P; H: S8 O; b
| 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data
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External memory
- @; k3 @4 b! f5 E5 Q, h | DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus
2 ^7 F3 I, |# M I& | | DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus
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SRAM or ROM directly connected to extension bus8 d# N# Q! \: V: D5 x: ~8 s
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Extension bus9 m) `; a' j; Z- q/ A1 P6 h
| Address space: 64 Mbytes × 3+ v7 q0 t+ V+ A" K' W) k. u# t
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Main on-chip peripheral functions
5 y2 Q$ e; [/ L& _/ f% j$ N3 ?3 r | Renesas Graphics processor(2D/3D)+ Q- ?. A! G3 G! l$ W
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Display control: outputs for two screens (digital RGB and LVDS)
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Video input interface4 C3 D8 |7 b9 _" d. K, _# l
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SD card host interface × 2 channels
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USB 2.0 host/function interface( z( p) d8 r5 {- }
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FM multiplex decoder7 f% }9 v8 y7 R- s$ B3 _/ r5 w
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Controller area network (RCAN) interface × 2 channels
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MOST interface module
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Various audio interfaces × 4 channels: B( p9 o9 R& W0 a- @# a1 x7 }
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Dedicated DMAC × 26 channels
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I2C bus interface × 2 channels# z4 X4 x, `0 d. Y! m
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Serial communication interface (SCIF) × 8 channels" h9 e& J- h3 N# I
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Remote control interface × 1 channel2 ?" R& G9 ]7 H( d: X# z8 S: {: `
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A/D converter (10-bit) × 4 channels
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Timer × 9 channels
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On-chip debugging function1 ], u& O' J7 U" c. P/ @% u
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Interrupt controller (INTC)
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Clock pulse generator (CPG): built-in PLL frequency multiplier4 {, t C7 V6 m( O
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Power-down modes( v/ L& a& x' i( |
| Sleep mode
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Module standby mode$ Z5 K. [, N6 G# m( g5 X8 M
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DDR-SDRAM power supply backup mode
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Package: b; M% }1 q/ m8 ^* W* Y
| 449-pin BGA (21 mm × 21 mm)! [& w2 h u5 {. w' Q* n: D
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