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| SH77722 (SH-NaviJ2) Specifications
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Type name
2 o- h+ [ c# K* i6 V6 e, O; O | R8A77722DA01BGV) d$ k; s, |- w3 w5 m J/ e
| R8A77722DA02BGV
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Power supply voltage
: E, z- V; M, Y% N | 1.15 to 1.3 V (internal), ; o$ y$ V& i! r
3.3 V and 1.8 V (external)# d7 }8 V. \0 G6 j- W
| 1.2 to 1.35 V (internal),
$ I! d. I" l2 S5 _. L2 |/ E/ ]3.3 V and 1.8 V (external), q/ Y( b- E+ ~' T u& \) t
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Maximum operating frequency
/ @# ?8 h0 L, K1 Q | 336 MHz
; j7 E) m5 q/ t* |2 H' J, s2 [ | 400 MHz
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Processing performance" j1 u, g# Y% P( P$ w& n
| 600MIPS, 2.3GFLOPS2 ?4 u: c/ u1 s4 q9 i0 }
| 720MIPS, 2.8GFLOPS; o d5 _! q4 Q7 s! g, U
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CPU core. R, z$ h6 T# n
| SH-4A core
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On-chip RAM
/ B$ [: \/ U. @, S8 U+ A' c4 z/ t | ILRAM: 16 Kbytes, Q: j5 [- ~# M \
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Cache memory
4 }" j' K, \- L0 x% A. ?$ s2 r9 V) ~! { | 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data
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External memory, q7 [5 d. r0 e2 `, R
| DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus
J/ F6 @4 {! e$ b | DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus
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SRAM or ROM directly connected to extension bus$ k' F; b' w# T. S# H4 E4 g
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Extension bus. X$ R+ [$ t! q- u0 T. ?+ b9 E
| Address space: 64 Mbytes × 3
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Main on-chip peripheral functions
) Q: K) Z* Y. ] | Renesas Graphics processor(2D/3D)1 ?. N) v0 p' i+ `* j1 d
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Display control: outputs for two screens (digital RGB and LVDS)% I, E5 K2 M, p# J8 o4 v, V
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Video input interface
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SD card host interface × 2 channels
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USB 2.0 host/function interface& s! l; Q' R* L# X. K
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FM multiplex decoder
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Controller area network (RCAN) interface × 2 channels
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MOST interface module
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Various audio interfaces × 4 channels
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Dedicated DMAC × 26 channels( _, ]7 C7 R2 _/ m7 F# j
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I2C bus interface × 2 channels
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Serial communication interface (SCIF) × 8 channels
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Remote control interface × 1 channel7 t4 v3 J) a, H! w: g
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A/D converter (10-bit) × 4 channels1 n* C, V5 m0 D0 f
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Timer × 9 channels
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On-chip debugging function D4 H4 M4 p1 N$ V5 s0 q; q# p E' W
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Interrupt controller (INTC)% j5 d0 ?8 q6 Q7 i/ \
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Clock pulse generator (CPG): built-in PLL frequency multiplier
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Power-down modes. K3 J' b+ }) J: w
| Sleep mode) Z& Y( }, Z/ H( U
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Module standby mode
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DDR-SDRAM power supply backup mode
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Package
# Z4 F: N+ ~0 _6 s, X | 449-pin BGA (21 mm × 21 mm)% |" x) Z' O3 s; e# I6 h6 ]
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