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Sponsor Z6 b, y3 J/ y
Test Technology Standards Committee of the IEEE Computer Society
/ R" b: p+ V7 @" o- r$ m0 z5 D4 ^Approved 14 June 20010 m( K/ R4 G7 {3 x
IEEE-SA Standards Board
1 Y# j5 x" I" D9 U8 VAbstract: Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and) G5 |' l8 \3 Q" b7 ]$ s; J: Z
support of assembled printed circuit boards is defined. The circuitry includes a standard interface) n1 h6 U4 G4 C- J
through which instructions and test data are communicated. A set of test features is defined,
8 W1 p& o, \! z- Lincluding a boundary-scan register, such that the component is able to respond to a minimum set
/ o) J. z% ^' `( wof instructions designed to assist with testing of assembled printed circuit boards. Also, a language
" d6 T$ M/ o! T1 @- [- E! T2 `8 Zis defined that allows rigorous description of the component-specific aspects of such testability features.) T2 X9 J' b- @! i+ K
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Keywords: boundary scan, boundary-scan architecture, Boundary-Scan Description Language,
- I- l5 M! M7 @8 P6 eboundary-scan register, BSDL, circuit boards, circuitry, integrated circuit, printed circuit boards,
+ n& ~! `& K+ I1 r; P0 QTAP, test, test access port, VHDL, VHSIC Hardware Description Language
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