Flip chip Manager level in China mainland

Achris

We are searching for flip chip R&D mgr, process mgr, project mgr for a well-known assembly and test house located in Shanghai, China. Below jd is for process mgr. Should you have any questions or concerns, please contact me by achris@edachr.com, 86-21-63203354, Achris Shen, we are a professional job-hunter company in semi market in China.
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Purpose of the Job (Why the job exists):
0 N# Z' {  `% o) f5 T0 a$ p% ~9 |1.        To define and develop new packages and technologies through benchmarking and interaction with PLM.
2.        To manage projects for on-time development through effective resource allocation and planning for rapid deployment of new technologies and products.
4 A9 s2 S1 C5 S4 j3 z+ w9 m3.        To transfer enabling technologies and products to relevant factories.
4.        To support and coordinate customer programs through interaction with customers and upper level management
4 ^2 s* {& r* `2 A# q, F5.        Make a plan or roadmap for future demand in market or customer.

' o2 `+ p% q. [, S+ y" HKey Job Accountabilities (Actual daily deliverables):
1.  Communication with customers and Emerging technology/PLM.
* r# u9 d8 G+ N9 T! r2.  Coordinate cross functional team activities
3.  Assign and review each engineering tasks and plans, or all project tasks and plans of project manager
$ h+ k& ], r, s. A6 E) c2 d4.  Ensure key deliverables are met for each stages of phase development procedure.
! j+ G1 ]9 d3 |! H* l- O3 Z% a5.  Update and discuss key issues with upper level management
6.  Adjust plans and update / modify current activity / engineering direction based on engineering data.
7.  Patent infringement search & IP generation
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* o' S! N( V1 ?2 ^3 I5 G Reporting Relationships
, R: A4 ]) g' P& }; n4 eReport to Director
" S! k# f* e6 Y% \MTS, Senior Engineer, Engineer reports to this position
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Required Experience and Qualifications
: A3 V2 z9 c% n- K1.        Minimum 8 years experience in FlipChip in both unit or strip form both as a similar position in a high volume and highly auto semiconductor operation.
2.        Flip chip process integration experience (Die saw, FCA, UF, Molding, SBM, Marking)
4 p5 \0 a  W, \6 P  K' g( N; @& J3.        Wafer bumping process