[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

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因為無法回覆, 所以開新文回答....
ABT={2'b00, DATA, 4'b0000};
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Verilog 常用的operator
– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
  v3 O; X7 U" A% b% i. o* G$ q3 p– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
) R4 r& r' _3 G' h8 p– Logical operators: !, &&, ||
– 2’s complement operators: +, -, *, /, %
– Relational operators: >, <, >=, <=, ==, !=, ===, !==
– Logical shift operators: >>, <<
– Conditional operators: ? :
, g! G/ Y4 F) p6 R– Duplication operators: {n{ <exp> <,<exp>> *}}
7 H2 \7 B5 }4 p– Concatenation operators: {}
* \% n0 |2 ^9 G( `給你參考一下