[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

因為無法回覆, 所以開新文回答....
) f+ V# ^# f" _! A2 Y. B/ \3 FABT={2'b00, DATA, 4'b0000};
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Verilog 常用的operator
4 w& y" k' n' {! e7 [– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
– Logical operators: !, &&, ||
% `( Q2 R+ F* d# b; f1 g/ [– 2’s complement operators: +, -, *, /, %
– Relational operators: >, <, >=, <=, ==, !=, ===, !==
+ z- ]# N' `" @9 l7 c– Logical shift operators: >>, <<
– Conditional operators: ? :
– Duplication operators: {n{ <exp> <,<exp>> *}}
* \& B& c. l4 `4 b– Concatenation operators: {}
& k: N& k( C3 F% ?給你參考一下