Circuit and Layout Co-Design for ESD Protection in BCD

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Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
* r3 k3 @8 ?3 T, ^
Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

Abstract—The n-channel lateral double-diffused metal–oxide–
5 X5 P. m( W' u$ Q* Wsemiconductor (nLDMOS) devices in high-voltage (HV) technologies
" Y7 P0 A9 O' j: c+ p2 q5 Oare known to have poor electrostatic discharge (ESD)
robustness. To improve the ESD robustness of nLDMOS, a co-design
method combining a new waffle layout structure and a trigger
: i9 G, F4 A, O; Y) P; k, B( Bcircuit is proposed to fulfill the body current injection technique
in this work. The proposed layout and circuit co-design method
on HV nLDMOS has successfully been verified in a 0.5- m 16-V
9 j' C( G) @! t! @1 l7 sbipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
process without using additional process modification. Experimental
: x$ N* ~& Q# Y+ z' z. J  Eresults through transmission line pulse measurement
- ]6 |( v3 j. H& d4 ^; kand failure analyses have shown that the proposed body current
% C' g( j3 Y5 a& _) j9 Z9 a0 M$ tinjection technique can significantly improve the ESD robustness
3 s, C8 t* ~+ ~5 \  j5 M$ lof HV nLDMOS.

3 t+ b4 A  Q1 F' ]& @' {+ sIndex Terms—Bipolar-CMOS-DMOS (BCD) process, body
' n# o7 t* A5 v9 ccurrent injection, electrostatic discharge (ESD), lateral double-diffused
" i6 s2 h! E5 I8 dmetal–oxide–semiconductor (LDMOS).

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