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實驗平台~; U3 e/ f* }/ {- w! q5 w
「Terasic」Altera DE0 多媒體開發平台,Cyclone III 3C16 FPGA$ R. |, d# N2 g" g2 v
在建構的過程中(僅放入cpu跟memory ip)% h' N! {) m1 Q. C- [, Y/ }
no reset vector has been specified for this CPU2 v5 Y) R7 y ]+ A
no exception vector has been specified for this CPU
9 R9 @& ]0 y4 i/ S: _$ |; G這兩個訊息,沒辦法完全消除,這兩個一定要消除嗎( V7 q9 t! F B9 A
試過
3 W7 V0 E4 Z) y# S/ Don chip memory) U/ s6 e6 q2 Q$ m7 z
sdram
" j, B; K* S" ?7 M$ @用上面兩個去試過所有可能的組合(mem/mem,sd/sd,sd/mem,mem/sd)8 R0 h1 j+ G4 {8 p0 r$ D
no reset vector has been specified for this CPU
0 N; f/ o/ ?8 e% \: ~no exception vector has been specified for this CPU
4 U; t1 U" b. Y7 p總是會有一個沒辦法去除(先選的訊息會被消除); G, J6 @2 k; e4 P/ M0 H
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有人有在玩10.1版嗎?請多多幫忙~~
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目前打算~改用10.0sp1跟9.1sp2試試看
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THX~ |
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