Cortex-M0+ IP Core

sinoicboy

6 N6 B1 \! A0 E+ {! t4 Y
( z8 P( ^% s+ e4 f! E

iconstart@gmail.com

                                  AR085-DA-70000-r0p0-03rel0/
. m/ G! P( u7 j  k# r4 X                                  AR085-DA-70000-r0p0-03rel0/doc/
                                  AR085-DA-70000-r0p0-03rel0/doc/ARMv6-M_architecture/
4af79e0557cc9c6863c2eab0f890aaad  AR085-DA-70000-r0p0-03rel0/doc/ARMv6-M_architecture/DDI0419C_arm_architecture_v6m_reference_manual.pdf
, |9 d" D5 }8 G% z3 S- C( B6 `8 |                                  AR085-DC-11001-r0p0-04rel0/
                                  AR085-DC-11001-r0p0-04rel0/doc/
% i; Y( C3 `2 x, h5 `2 A+ E                                  AR085-DC-11001-r0p0-04rel0/doc/errata/
; b2 L' T( Z; U4 O7 L! G57ce61d69a56fae9dff02a664dc0930a  AR085-DC-11001-r0p0-04rel0/doc/errata/ARMv6-M_Architecture_Errata_List.pdf
                                  AT590-BU-11001-r0p1-00rel0/
4 s1 p$ ?- c* l+ m  Ob2bb2db05b71fa9e2ecd4c2841c22f3f  AT590-BU-11001-r0p1-00rel0/Cortex-M0+_Product_Errata_Notice_v4.pdf
d305236940b52b92b81e8579435efe7e  AT590-BU-11001-r0p1-00rel0/Cortex-M0+_Software_Developers_Errata_Notice_v4.pdf
. S+ l$ c" @* c" G( C# ~2d80706f7a099ac4a9674908c50d730e  AT590-BU-11001-r0p1-00rel0/AT590-BU-11001-r0p1-00rel0.lst
7 R& u' S' i& d/ x. Q                                  AT590-BU-50000-r0p1-00rel0/
70404309a7929774e3bd8786e10771eb  AT590-BU-50000-r0p1-00rel0/ARM_Cortex-M0+_r0p1-30rel0_ReleaseNote.pdf
                                  AT590-BU-50000-r0p1-00rel0/logical/
! s' o& e7 `3 W% o* h% S                                  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/
                                  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/
80fe9cfaeb5e260f70aebfcac0bdf888  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_cdc.v
063cdb1c994aca1f31971a3d52da426d  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_sw_defs.v
17f0e782572ea85e916a26ef804106ac  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_jtag_defs.v
( V8 n; W" j4 z2 S% ^* @* Ndb6b0ced453f9ba83035ca0b2d31c55d  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_ap_mast.v
12e85d89d377ef33f7a41f5f49bf20f0  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_jtag.v
bb3812a6b967f1ffaa604a858064f1d6  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_top.v
2b71a63c5d6843c6a0c64972ca0a3483  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp.v
- P) x5 K1 J9 E4 f' Q) q5 v! F% ]fc6a96af9879ce4ccb0c150913d38ab5  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_ap_cdc.v
72017024f98163d43c2f77e920560bd3  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_ap.v
% A- f9 @' m+ l) q' n8 y6ca54cbd04210e471b30aaca343e1966  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_ap_mast_defs.v
. c  v7 g8 M1 g+ L& C- n764fcf3fa6ce572a3325f069a591baf6  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_pwr.v
- D2 U; U% ?" I5 D' {3ffb32cddb6a7e19f9f91e437f7ca59b  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/CM0PDAP.v
75d1d91ab79ae9e0e044ed1ef71cf03e  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_sw.v
                                  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/
                                  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/
95d54f552eade07ede322600da1f95c3  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_bpu.v
- B3 N- `) ~' j* D+ S8 o) o302c07875f4fc2cfe52c087ca6429cc0  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_matrix_sel.v
; G# X! K1 E  Y9 Z5 hfce226f9ab48e92ff074fcad3dec6728  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_sel.v
c00549e61aae47696609028230712dd6  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_ctl.v
ed481eab3481c71d4e2dc94531b88a3d  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_nvic.v
- K6 p5 M2 k1 i0 j% B+ L57a19fb958028b39c425e6ac68f882aa  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_top_sys.v
66bc815f02ad900042cec326a6679963  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_dwt.v
$ r0 T- K+ x5 X: T62d60f5f2bceb3ce3f82e8fcb48446ff  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_mpu.v
4b054567197e5f54d3bacf492271f4c9  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_matrix.v
4 @2 c$ [7 v: Ga436b897620bcd65a4f6f7d50345215e  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_top_clk.v

114142500

thanks! do you have source codes for M0? It‘s very great for sharing the code。my e-mail is 114142500@qq.com,thank you very much!