Time | Topics | Speaker |
13:00-13:30 | 報到 | |
13:30-13:40 | Welcome & Introduction | Jay Wang
Country Manager, Xilinx
Jerry Tung
Engineering Manager, TeraSoft Inc. |
13:40-13:50 | FPGA 軟硬體的協同開發設計
(Xilinx FPGA & MathWorks MATLAB/Simulink) 簡介:
Development Platform & Demo Booth Introduction | Jack Yang
Account Assistant Manager, ANStek
Charles Su
Engineer, TeraSoft Inc. |
13:50-14:40 | HDL 模型及 IP 核心的建構三步驟-以影像處理為例
(HDL Model for IP Core in 3 steps) 簡介:
1. Test Pattern Model
2. HDL Code generation
3. Interface for Zynq | Charles Su
Engineer, TeraSoft Inc. |
14:40-15:30 | 快速建立 Xilinx FPGA 專案三步驟
(Quickly Building Xilinx FPGA Project in 3 steps) 簡介:
1. System architecture Setup
2. Xilinx and MATLAB IP integration
3. Software development | Jack Yang
Account Assistant Manager, ANStek |
15:30-15:50 | Coffee Break 及實際操作演示 | |
15:50-16:40 | 利用 MATLAB & Simulink 加速影像視覺以及馬達控制之開發
簡介:1. MATLAB / Simulink 介紹
2. 工作流程導引: 從 MATLAB/Simulink 到 FPGA
(A guided workflow: from MATLAB and Simulink to FPGA) | Judy Yang /
Jerry Tung
Engineer/Engineering Manager, TeraSoft Inc. |
16:40-17:00 | Coffee Break 及實際操作演示 | |