關於cell-based 流程的DRC問題

ywchywch

請問各位大大
我用TSMC18的design kit作cell-based layout的練習，軟體是用encounter，大部分的步驟是依照CIC所提供的Lab去做，完成之後用我的GDS檔去做DRC，會出現下列的DRC ERROR，而且是M1~M5、via1~via5都會有這方面的error，因為error的數目頗大，不太可能用人工去debug，所以我想請問有經驗的大大們，能不能告訴我最大的問題點在哪裡？以及這些錯誤代表什麼？要如何debug比較適合？

9 E+ S4 ~3 M+ [& Y先謝謝各位大大了!!感激不盡!!

. v2 p5 Z$ g5 N8 X1. M2.W.1 { @ M2 width < 0.28
  INT M2 < 0.28 SINGULAR REGION ABUT < 90
}
  D% \" Z7 m, P) B+ g# R
2. M2.S.1 { @ M2 spacing < 0.28
  j( I# I) W/ ]# E6 _. w- {  EXT M2 < 0.28 ABUT < 90 SINGULAR REGION
}
# v, C' h' e3 g: h$ Y
3. M2.S.2 { @ Wide M2 (>10um) min. to M2 < 0.6 um
  M2_S5 = SHRINK (SHRINK (SHRINK (SHRINK M2 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
& G( p, N  C5 m( O- q  M2_G5 = GROW (GROW (GROW (GROW M2_S5 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
5 U( v+ g' {  U+ ]+ b' |  M2_Wide = M2_G5 AND M2

  M2_Exp = SIZE M2_Wide BY 1 INSIDE OF M2 STEP 0.196
  M2_Branch = M2_Exp NOT M2_Wide
5 m! B: y# ^5 {' p* X0 L% F, ?  M2_Branch_edge = M2_Branch COIN INSIDE EDGE M2
: C6 [* }6 X8 M  W6 C  M2_Check = M2 AND (SIZE M2_Exp BY 0.6)
  M2_Else = M2_Check NOT INTERACT M2_Exp
  M2_Extend = M2_Check NOT M2_Exp
& ^8 g6 b- C: S% L8 ~' }
  EXT M2_Wide M2_Else < 0.6 ABUT >0 <89.5 REGION
" I) ~0 T0 O( h; R  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 OPPOSITE REGION
& d5 n2 e" V6 V$ y  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 CORNER REGION
7 U9 f3 ^1 y8 o+ u) ?4 }  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 PROJ==0 REGION
  A = EXT M2_Exp < 0.6 ABUT > 0 < 89.5 SPACE REGION
6 k- e9 p1 O+ k5 @& S9 E  A NOT INTERACT M2_Extend
3 \5 a+ G, Z$ h' J4 r}
4. M2.E.1 { @ Min extension of a M2 region beyond a VIA1 region is 0.01 um
$ K+ o' ^/ [& p9 P   ENC VIA1 M2 < 0.01 ABUT<90 SINGULAR
1 w  H7 e5 |5 R   VIA1 NOT M2   
}
% M( r$ o1 G/ G4 V
5. M2.E.2 { @ Min extension of M2 end-of-line region beyond VIA1 region is 0.06um
. P! h! `5 {( f. i   X = ENC [VIA1] M2 < 0.06 ABUT < 90 OPPOSITE                // a narrow side
  W8 U& a2 k4 j   INT X < 0.26 ABUT == 90 INTERSECTING ONLY       // adjacent narrow sides
0 b2 a$ ~+ N1 L3 D}

1 w: P* i" s0 ^& D+ O( Q6. M2.A.1{ @ Min M2 area region < 0.202
  AREA M2 < 0.202
}
0 R3 D# D0 N) x+ M( v" w( _// Density check M2.R.1 included at the end of this file
// VIA2 checks
//=============

+ k# }" P- `9 b$ h2 S7. VIA2.W.1 { @ VIA2 must be 0.26 x 0.26 um
  A = NOT RECTANGLE VIA2 == 0.26 BY == 0.26 ORTHOGONAL ONLY
% L7 G8 Z. S) J/ A* Y& W' x  A OUTSIDE RNGX   // exclude from metal fuse protection ring area
& F) o0 ~8 X6 H- C+ b}

8. VIA2.S.1 { @ VIA2 SPACING < 0.26
) }8 g2 j8 L9 w  e  EXT VIA2 < 0.26 ABUT < 90 SINGULAR REGION
}

& p: D/ P, Z; `9. VIA2.E.1 { @ Min extension of a M2 region beyond a VIA2 region is 0.01 um
  ENC VIA2 M2 < 0.01 ABUT<90 SINGULAR
  I5 l& d% d  A0 |5 l$ x4 A) @/ h  VIA2 NOT M2   
( b8 P) H! P5 ^" V, R; s2 F% v3 l}
; Y6 X1 H  d' m+ G3 s4 L
1 ]6 W  r  n$ l- S' |10. VIA2.E.2 { @ Min extension of M2 end-of-line region beyond VIA2 region is 0.06 um
   X = ENC [VIA2] M2 < 0.06 ABUT < 90 OPPOSITE         // a narrow side
   INT X < 0.26  ABUT == 90 INTERSECTING ONLY     // adjacent narrow sides
* A: L" U$ ?. R+ G) Y0 _}

motofatfat

我猜你試用APR軟體RUN出來ㄉ
應該是相同NET ㄉMetal space 和 via extension
4 V  ]! a( g; h4 z) o2 t不夠的問題,通常會用 skill file 來修正

michael6172

我覺得你打電話去CIC問工程師會比較快吧 ...