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8 Failure Modes, Reliability Issues, and Case Studies 228! I& D9 m# j3 |; @. A+ q4 y( [
8.1 Introduction 228
3 q! A7 i' @. Q0 m$ J$ ~8.2 Failure Mode Analysis 229
$ B |. C% o! x2 L2 J' U% d8.3 Reliability and Performance Considerations 2386 m, D0 Q Z/ w% m
8.4 Advanced CMOS Input Protection 239# A( o1 k" M9 h9 L1 q0 U p
8.5 Optimizing the Input Protection Scheme 242% J/ L- s: u9 g+ C
8.6 Designs for Special Applications 249% V; x* H6 f. J2 E3 E: E
8.7 Process Effects on Input Protection Design 253" ^- y& E5 d% R
8.8 Total IC Chip Protection 255- O6 z; `% f/ w" l) s- E, o& V
8.9 Power Bus Protection 256% \. l6 b# B4 Q) w
8.10 Internal Chip ESD Damage 258
0 l. s5 M5 z8 P& t4 @8.11 Stress Dependent ESD Behavior 263, `9 `* k; i P) o" O
8.12 Failure Mode Case Studies 267
3 l; K/ l- C8 K8 V8.13 Summary 271
9 Z) \6 T- T+ o4 OBibliography 2721 F/ U8 k6 q3 J3 C
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