the gate line of CMOS power cell problem

rfbeginner

Hi, Now I'm designneing the RF CMOS power cell, I want to design the proper gateline netwirk with EM simulator, but found that it is so sensitive to the conductive substrate? (I mean when the sub is setted with cnductive, the gain will degerate a lot but when it is setted with nonconductive, that gain looks like good), bdesides, I found that when i put metal (ex.M1) under the gateline, for some foundrym it will be good, but for some foundry, it doesn't, looks like so wired! whi can tell u something about it? who has some experience? Pls give me some helps! thank u!

CHIP321

不知道我理解的是否正确，因为的确在某些代工厂商所提供的规则文件中，对连接文件的定义有偏差，并没有按照严格的Connect关系来定义连接。所以这是一个严重的问题，只能通过重新定义设计规则文件中的相关项来解决。