十項全能 vs. 三項鐵人？Layout達人如你未來最需要加強哪三項吶？

chip123

佈局工程師應該成為十項全能冠軍!?  26 / 25046
佈局工程師必須要多懂一點其他專業知識和提升能力？
內行的人看門道，外行的人看熱鬧？

) [: H9 @% f: W- _) l9 _- slayout engineer 的職場競爭力、專業知識地圖、被利用價值...？

nebula0911

其實以我自己 layout 的經驗來說,只有 APR & fully layout 之分,其他都是架構在 fully layout 中,只是強調的重點不太一樣.
6 T9 |  g# b. g6 l以個人來說,我比較想學的順序是:1. 懂不同的command file編寫  2.懂專案規劃floor plan  3.懂不同的APR操作和設定.
2 a/ l. N2 k  g% ~, z; X因為了解 command file 的編寫方式,能夠幫我在 layout 的同時,提醒自己一些注意事項,減少debug的時間(當然是已經熟記& 符合rule的狀態下);
懂專案規劃floor plan ,可以避免因規劃不當,導致 block 因需要配合其他人的而需重 layout 的情形,少跑一點冤枉路;
學習 APR 是想讓自己在 layout 領域中更加完整;必竟多學一樣技藝在身,就多一項優勢;至少在整合 chip 時,有小問題就可以處理,不需要處處麻煩別人;提問問題時也不會雞同鴨講.
6 O, k9 w- {' A7 v5 G2 z+ c這是個人的一點想法,供大家參考參考!!

semico_ljj

楼上说得不错

tk02561

招聘公司：A famous IC company
) f' m& x8 w# a% }' Q1 l1 B招聘岗位：Layout Designer
" ?5 Q: j7 ^% o- n' f; W5 K工作地点：Shanghai
. A" d( V' j' l. `岗位描述：

0 e7 e9 n, x2 _6 K2 `Work effectively with designers to understand key layout constraints Floorplanning and layout of custom analog cells Run Assura DRC, LVS, RCX at block and chip levels Hold layout reviews of completed cells Solid understanding and experience of 180nm, 130nm, 90nm, and deep sub-micron processes, IC layout methodology/techniques. Strong experience in CMOS/BCD process and custom analog layout. Experience with Cadence layout and physical verification flow (Assura) 2-5 years of layout experience Understanding of layout considerations pertaining to matching, noise shielding, and latchup in analog, mixed signal and digital circuit Experience in performing DRC, LVS, RCX, LVL, and other complex checks needed for tapeouts Handling of large place and routed blocks and integrating it with the analog blocks is a plus knowledge on putting large complex mixed-signal chips together a plus Excellent communication and interpersonal skills. · Experience with analog mixed signal circuits

ranica

招聘公司：A famous analog IC company
招聘岗位：Mask Designer / Physical Layout Designer
2 r0 D' o9 h9 `* c7 t3 y% ?工作地点：Hangzhou

岗位描述：
: Z3 u; T6 w/ y1 hPosition Overview XX Technology Corporation is seeking an enthusiastic Mask Designer / Physical Layout Engineer in our Hangzhou, China Design Center. We develop a wide range of high-performance power, analog, and mixed-signal ICs using our unique Bipolar, Bi-CMOS, and CMOS processes. We compete in a wide range of markets including:

• DC/DC Converters • High Resolution Data Conversion • Interface Products • Portable Power Management • Hot Swap Controllers • High Performance Amplifiers and References • Automotive Electronics

6 M! U' Y% Q* E! JResponsibilities include (but are not limited to):
• Layout schedule estimation.
, M" V! l% J1 C7 A: F7 V! |1 p• IC layout floor planning.
1 E' Q+ P8 _3 Y: [• Layout of analog and digital circuits.
• Cell level verification and parasitic extraction.
• Chip/Top level routing and interconnect.
• LVS and DRC checks using Cadence Dracula and Assura.
5 G4 o5 m8 k9 `# N0 H3 n7 N• Tape out/Stream out/PG.

ranica

职位要求：
$ C" T/ G" \2 s( l3 rRequired Skills The ideal candidate must have the following key requirements for this position:

/ W; _. N/ e# i. n$ j1 q2 }• Bachelor or master’s degree in Electrical Engineering or related major.
/ u5 l+ Q5 J- T• Five years of relevant IC layout experience.
• Strong background in analog layout.
' E8 K  R# h1 A) e• Familiarity with Cadence tools (Virtuoso, Layout XL, Assura, Dracula).
7 n% X- N1 q1 i# V" `# v3 X) g• Layout experience with bipolar, CMOS, and BiCMOS technologies.
! I% m5 T; f' S; s; z# _0 m) A. m• Working knowledge of Linux operating systems.
• Experience with full chip layout including PG to the mask shop.
- K/ m# `: L7 I5 Z2 S8 X2 U1 R& G/ A• Knowledge of semiconductor device and fabrication principles is a plus.
" K! _- D! }7 }9 q- M+ W• Ability to work independently.
* r- p6 i9 y) B% q' \• Great attention to detail, communication skills, well organized

ranica

招聘公司：A famous European IC company
8 W% j- z" G9 H* W. \  V招聘岗位：Layout design engineer
; w  U+ G% [6 e工作地点：Shanghai
9 v' |* K2 i/ t% \- W0 m) M9 L
岗位描述：
6 f4 O6 u4 J. y. d7 T) j  URoles and Responsibilities Full-custom layout of analog and mixed-signal circuits Estimation of efforts and schedules for layout projects Floorplan generation for analog layouts Optimization of analog layouts for low parasitics and low area Close cooperation and interaction with international teams

% ?( I9 E; u* v9 N4 v$ ~# E4 h职位要求：
Qualification Requirement (e.g. Education, Working Experience, Knowledge, Skills, Language, Competence, etc) Bachelor or master degree in Electronics, Communications, Computer Engineering or equivalent, 3+ years Experience in analog full-custom layout (CMOS) Experience in running DRC, LVS, and PEX preferably with Cadence Virtuoso Understanding of CMOS process flow Self motivated, excellent communication skills and team spirit English written and verbal Willingness to work and interact in international teams

liu.leon

基本上前九項,layout 都應該都要會,不一定要熟練到精,應該沒有layout十項全能

但第十項,就不一定了,因為有些公司RD會自己plan ,你最多建議RD 你的看法而已,

. R5 ]. @2 M: @8 l# f) b不然丟一句話"IC出問題誰負責"~~不就吃不玩兜著走嗎??

鄒佳佑@FB

未來越來越精密的製程,數位APR部分相對未來越占更高的比重