14.H.264,中可變方塊大小移動估測Algorithm 及VLSI IP多重圖框移動估測Algorithm 及VLSI IP 1/4pixel 移動估測Algorithm 及VLSI IP CAVLCVLC Algorithm 及VLSI IP. Intra 圖框整合Algorithm 及VLSI IP.. N) N: }( E# k5 O) @
| This patent presents a fast algorithm and its VLSI design to implement the variable block size motion estimation for H.264 system. The fast algorithm is proposed based on hardware-oriented concept for regular VLSI design. Simulations show that our proposed algorithm can save 88%~94% motion searching time under H.264 program JM8.6 while PSNR only decreases about 0.02dB in average. Based in the fast algorithm, the real-time VLSI architecture is proposed with parallel structure. The hierarchical method is used to reduce the design complexity, which the timing schedule is controlled with particular pipeline flow. The chip can compute 41 vectors for various block size during 256 cycles as using only 96 PEs. Comparisons with other VLSI architectures, we can offer higher processing speed, lower memory bandwidth and lower circuit complexity.The fast multi-frame motion estimation consists of the adaptive full-search, three-step and diamond searches with using content adaptive control. The decision criterion is proposed to achieve better rate-distortion for H.264 system. The experimental results show that the speed-up is 6~15 times compared with the full search method while the PSNR value is slightly degrading. The proposed algorithm can achieve faster speed and lower bit-rate compared to the competing algorithms. | □技術授權
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| 3G手機, 多媒體, 數位電視, 數位攝影機
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15.運用於監控系統之MPEG-4 coder 及 物件分離技術.
. e8 ?) T X0 y6 O" h! I$ u6 [7 h6 @ | In this patent, we first present an adaptive full-search algorithm based on temporal correlation approach.* I% Z! i* h- S! F) T
The efficiency of the proposed full search can be promoted about 5-20 times as comparison with the conventional full search, and the searching accuracy is kept.: _5 Q0 q9 s: ]
Based on the proposed full search algorithm, a real-time VLSI architecture is developed. The computational kernel is designed by PE modular that can be regularly expanded for high-speed system. The gate count of chip is about 8k when the computational kernel is expanded to 8PEs for MPEG-II coding application. The processing rate of proposed chip can achieve 53k blocks per second for searching range from –127 to +127, and the power dissipation is about 30mW with 0.35um TSMC technology. | □ 技術授權 b) P/ J3 o' B7 M j
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16.數位電視錯誤資料重建Algorithm 及VLSI IP.
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| The digital TV broadcasting system adopts the video coding to save the channel bandwidth, but the decoding image will appear distortions as the bit stream suffers from damages. This patent presents an error concealment processor to promote the performance of TV receiver. An efficiency error-concealment algorithm is advised with the adaptation of the spatial interpolation and the temporal prediction to reduce the non-matched error for high motion regions and achieves high resolution for still or low motion regions. Based on the adaptive algorithm, a real-time VLSI architecture is developed with a pipelined-flow structure and parallel processing. The complex processing schedule for the error concealment processor is arranged to integrate video decoding systems for real time implementation. The chip occupies about 27k gates and includes one on-chip line-buffer. The silicon area is about 9mm2 with TSMC 0.35um process, and the throughput rate can achieve 50M pixels per second. | □ 技術授權+ h) w3 }6 ~4 m+ Y: w+ I
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17.攝影機DSPAlgorithm 及VLSI IP./ 色彩內插處理器及其色彩內插計算方法, 區域式文字、影像之光源平衡處理方法
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| This patent proposed a color interpolation technique for a single chip CCD (charge-coupled device) with color-filter-array format. Using edge direction weighting and the local gain approach, we reconstruct color components in high accuracy but low computational complexity. Simulations result that the proposed method outperforms the other techniques to which it was compared. Based on the new algorithm, a cost-effective architecture consists of pipeline schedule for real-time operations. With time-sharing method, this architecture can interpolate various colors using a common computational kernel. The circuit complexity can be efficiently reduced. The prototype of color interpolation processor has been successfully verified with a FGPA device, and an ASIC chip is also designed with TSMC 0.35um. The chip core uses about 10k gates and two line-buffers. | þ 技術授權
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18.視訊雜訊消除DSPAlgorithm 及VLSI IP
. i& ?- m& h) s( l6 ]- |: ~ | This patent proposes an efficient noise-removal algorithm using an adaptive digital signal processing approach. Simulations have demonstrated that the new adaptive algorithm could efficiently reduce impulse noise even in highly corrupted images. In order to achieve real-time implementation, a cost-effective architecture is proposed using a parallel structure and pipelined processing. The proposed processor can achieve the throughput rate of 45M pixels per second using only 4k gates and two line-buffers. Unlike median-filtering chips, this processor provides better filtering quality and its circuit is much less complex. | □ 技術授權
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19.產生高效率灰階之電子浮水印方法
0 G: m* m- ?% h* E | In this patent an efficient watermarking algorithm is presented with two-layer hidden for gray-level image watermarking.
8 J9 ^& H6 o! ~5 h2 B/ n5 b9 J2 XIn the first layer, the key information is found by using the codebook concept. Then the secret key is further hidden to the watermarked image using the encryption consisting of spatial distribution in the second layer." T. v3 L. `8 x2 v) g
As a result, the watermarking information becomes perceptually invisible in the watermarked image. Moreover, the gray-level watermark can be extracted by referring key parameter rather than original image. | þ 技術授權 $ {6 H a/ [/ L! ]: k( F
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發表於 2008-11-8 11:35:01
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