Cadence Announces Encounter Digital Implementation System

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Cadence Announces Encounter Digital Implementation System with EDA Industry First End-to-End Parallel Processing Flow

9 a) F2 P0 n( f9 b# X0 S4 vUltra Scalable RTL-to-GDSII System Marks New Era of Productivity for Design Closure and Signoff Analysis in Advanced Low-Power and Mixed-Signal Designs
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SAN JOSE, Calif., 03 Dec 2008
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Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, has launched the Cadence® Encounter® Digital Implementation System, a configurable digital implementation platform delivering incredible scalability with complete support for parallel processing across the design flow. The system also brings an ultra-efficient new core memory architecture delivering higher-performance, higher-capacity design closure for single CPU operations. With this new system, designers are reporting dramatically improved design time, design closure, and faster time-to-market for advanced digital and mixed-signal devices.

0 u; s. @8 u9 j1 f  P4 `3 XAlong with enhanced performance and capacity, Encounter Digital Implementation System offers new technologies for silicon virtual prototyping, die-size exploration and RTL and physical synthesis, providing improved predictability and optimization in early stages of the design flow. In addition, multiple new and enhanced implementation and design closure technologies are being introduced, including automated floorplan synthesis, end-to-end multi-mode multi-corner optimization, variation-tolerant and low power clock tree and clock mesh synthesis, high-capacity placement and optimization, 32-nanometer routing and manufacturing-aware optimization, signoff-driven implementation, and flip chip design features.
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"Tilera's TILEPro64™ processor includes 64 general purpose cores each operating at up to 866 MHz with total chip power consumption under 20 watts, thus putting challenging requirements on timing and power," said John F. Brown III, VP IC Engineering at Tilera. "Encounter Digital Implementation System brings together all the related tools under one interface with easy data-sharing and powerful debug capabilities. We can now converge early in the chip development process, achieving faster design closure and meeting aggressive time-to-market goals for our networking, wireless, and digital multimedia applications."

Using Encounter Digital Implementation System designers are able to achieve extraordinary levels of predictability, productivity, scalability, and flexibility from its unified and automated implementation environment for high performance, high-capacity design closure; low power, mixed signal and advanced node design; and signoff analysis. The extensibility and integration of the Encounter Digital Implementation System helps designers to achieve rapid technology adoption, and a faster, higher-quality ramp to volume production.
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"As a leader in SoC design services, Faraday has always been committed to designing chips that are not only high performance, but high power-efficiency as well," said Kun-Cheng Wu, Director of Design Development, Faraday Technology. "Encounter Digital Implementation System's low power technology exceeds our expectations in delivering a low-power implementation flow. The CPF-enabled Cadence Low Power Solution provides a full front-to-back solution that helps us significantly reduce power consumption in our designs."
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"We have been very successful in using the Cadence implementation environment to develop and tapeout our challenging mixed signal designs," said Dr. Daniel Van Blerkom, CTO at Forza Silicon. "Our corporate goal is to exceed our customer's demanding time-to-market objectives, and Cadence has helped us achieve this goal. Using the combination of the Encounter Digital Implementation System and the Virtuoso® custom IC design platform has significantly improved our design efficiency. This has enabled us to deliver high quality mixed signal circuits and designs to our customers, while meeting our aggressive schedules."
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The Encounter Digital Implementation System’s advanced node technologies, including litho-, CMP-, thermal, and statistical-aware optimization, make it an uniquely capable solution for leading-edge 45- and 32-nanometer designs – those with aggressive design specifications including 100 million or more instances, 1,000-plus macros, operating speeds exceeding 1GHz, ultra-low power budgets, and large amounts of mixed-signal content. The system provides comprehensive manufacturing-aware and variation-aware implementation, and an end-to-end multi-core infrastructure for fast, predictable design closure.
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"Built on a strong portfolio of production-proven core technologies, the new Encounter Digital Implementation System ushers in a new era of productivity for digital IC design," said David Desharnais, group director of the Cadence digital implementation group. "It leads the way in multi-CPU performance, capacity, integration of design closure, low-power, mixed-signal, and advanced node design features and real-time signoff analysis necessary to reduce time to market and risk for our customers."
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Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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For more information, please contact:
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" B8 w9 P" E0 b9 t/ \2 y: A' RDan Holden
" ~. L2 @2 v0 [2 tCadence Design Systems, Inc.
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holden@cadence.com

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Cadence益華電腦發表Cadence Encounter數位設計實現系統，這是可架構(configurable)的數位設計實現平台，提供絕佳延展性(scalability)以及涵蓋設計流程的平行處理技術的完善支援。這個系統也實現了超高效率的全新核心記憶體架構，為單一CPU的作業提供更高效能、更大容量(capacity)的設計收斂。除了更佳的效能與容量之外，Encounter數位設計實現系統還提供全新的矽晶片虛擬原型建立(silicon virtual prototyping)、晶片尺寸探究與RTL和實體合成技術，在設計流程的初期就實現更高的可預測性與最佳化。此外，也導入了多項全新而且更先進的設計實現與設計收斂技術，包括自動化平面佈局合成(floorplan synthesis)、前段到後段multi-mode multi-corner optimization、變異容限(variation-tolerant)與低功耗clock tree和clock mesh合成、大量佈局與最佳化、32奈米繞線與具製造導向(manufacturing-aware)最佳化、sign-off導向的設計實現，及覆晶(flip chip)設計功能。