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Standard Cell 的 Data Prepare 的過程我會去做 axgDefineWireTracks
# G3 m7 Z; ~5 p然後再做 axgCheckWireTrack 來 check wire track, 但是做完 axgCheckWireTrack
" g* m; B! u% _& d4 ~4 o7 B之後卻有如下之 Meaasge:
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******** Pin Access Analysis *******
7 m( C. A3 [+ h2 ~3 P$ u% W) G; C** # Cell Masters = 1000) u" q; I: X4 c, b
** # Ports (logical) = 2500( R3 y _4 I8 D2 h" D3 j
** # Pins (physical) = 2500
' V3 Q2 t4 u& v. K1 S" _** # Pins with no good access point on Grid (V&H) = 5 ( 0%)" Y4 l( ? ]4 U @) P# p
** # Pins with no good access point on Ver-Grid = 5 ( 0%)/ i. o* a4 U9 Z. A* R T" k. J
* F3 K2 k. y- N' w. ?1 u$ P8 H: u
請問下面這兩句是代表什麼意思呢?- v7 Z# j1 l" v T
** # Pins with no good access point on Grid (V&H) = 5 ( 0%)8 ~) Q0 `" X- x2 v4 J/ r& t' C0 W
** # Pins with no good access point on Ver-Grid = 5 ( 0%)5 E6 k. c" Q6 a- K# j# C- B
. v$ e+ ]( m9 y; {5 ]0 \2 \若是代表有錯誤的話是否要 Fix 呢? |
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