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Software Support
$ T# G# [2 x0 D( r9 r* y% I3 u- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.
4 \2 o% i* a0 i# T* l
$ M: \, Y( h3 f3 H$ bPlatform Support 4 k' l+ E3 Y. @* `
- Microsoft Windows XP (32 bit) , r, X% q5 x; n( }5 G
+ d2 q6 V8 M% C8 L2 [, l
Device Support
9 _+ u& G+ p( j: A3 I- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported.
( r4 w# L, z$ A( L, F6 p1 ^; p( Q- O8 R4 P' n8 e% q" B. t
New Features 2 @$ c: Y5 S0 q1 I9 j
General New Features and Changes
: A6 T- l1 x* e2 J% |- Supports "Create New Memory Part" for all the designs. 3 P& f% t, h- S; K. }5 N
- DDR and DDR2 SDRAM designs for Spartan-3A.
+ b% X8 Q! A9 P0 T* @- DDR SDRAM is supported for Virtex-5. ; s$ M# ?5 e2 w/ T( c
- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. - M( E( k( N% J& e
- MIG now pops up the design notes specific to the generated design. & s* q8 ^) G* @( M- A) I+ B) h
- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs.
1 b- N5 g2 p' H. ]: t- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. - I; S: k! i- i- W2 O1 C+ a
- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2. ( o Y, ~) `: _8 |% E/ B1 A
- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A. - l a7 m' j5 j
- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST". 9 q, l6 n1 N% Q& t7 h9 n
- Default setting "DCI for Address and Control " is changed to "unChecked".
0 M8 v" u4 ~7 ~# ^' P- Frequency slider is changed to editable box in the GUI.
. d# D7 P ^) p. v6 Y6 k6 [; p& s/ A- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
8 L" y0 i0 [9 Z4 f4 i- Removed console window when running MIG through CORE Generator.
6 }3 [' {2 P3 e- WASSO table (Set Advanced Options) accepts only numeric characters. ' b- n Q: |* K
- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32.
* c4 @) @0 B% w: o9 D8 J. v& [) ]- Provided web links for all XAPPs in the docs folder of the designs.
% E9 ]9 V. L5 ~/ z1 c- Provided link to Data Sheet instead of Log Sheet in the output window. " B% C( l. @4 m% U( u) L5 J
- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window.
8 Q, U! I* w. j0 z- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. 6 c3 z0 h; y4 \; ~, h/ {% V
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.
) w7 n+ Z9 A+ }4 H0 ^1 ]% ~6 Q; z( S; {. I5 g' v! |5 b/ i+ B. }
Virtex-5 New Features and Changes
1 h" ]+ m. e9 W4 P t9 E% ZDDR2 SDRAM
; I( m. |+ E2 ~- New controller with several high-performance features. All the features are described in detail in the Application Notes.
; W0 l. A, @* |" q. F, T- Enhanced data calibration algorithms for higher reliability.
; u3 g5 k- t0 M* f8 a- Bank Management feature is supported.
/ U- k: _; a; [6 w f. Z9 y; i$ }8 Z- Supports VHDL.
/ z* O8 j8 F" k$ @' W( @; o- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear. % f. X& d$ F/ ~% q6 C
- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus.
7 n i8 M: N( Y- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions.
7 P' B1 A) T2 [a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. . h/ x, v4 R0 ~& @ G; o1 Q
b. WASSO is applied to all the memory interface signals.
- C9 A2 P) ~; T, C3 j: ?c. Signals such as "Error" outputs are not part of the WASSO count. , J) q4 Q y/ Z! u8 R- c6 S" U
2 S v9 P1 D; a0 P1 `2 _DDR SDRAM " ~2 q+ b5 Y/ |$ E
- This is a new design for MIG. Supports Verilog and VHDL.
2 r" \9 f8 h1 a+ g0 A% G. @- Bank Management feature is supported. * L. E& _" @' |+ ]& e; o- v
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. 7 W2 B6 t) p6 y0 W" t" |
0 X1 f8 I& s- l6 _5 D
QDRII SRAM " r; ]& }. o9 J" k0 M0 c8 ^- o2 v
- Added support for VHDL.
6 }# {& U" |# ^' Y; M7 c, r- Added support for 72-bit designs. 7 P$ ?4 X6 @0 ^, U4 O
- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay.
; k' G( |1 l. o. a# Q: V1 B- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 . E4 L% ^. g5 l9 u( V5 {4 I' u$ p
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons.
F$ Z$ `; n9 u* S8 E, f- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
& F& ~; |0 m4 d( x8 B- \+ m+ F1 Fa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 8 M% E! G2 r8 a
b. WASSO is applied to the output signals only. , r& C7 J; i0 X+ j
& F2 L7 _4 `# A6 t5 _0 |
Virtex-4 New Features and Changes
3 N, |; m* U( Z# {0 D9 MDDR2 SDRAM Direct Clocking
. S U- U N) ^5 `( @- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design. ' Q6 G# z) [5 h* Q. p0 G
- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. & m! H5 @% v6 K( ]' w8 l2 U
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
5 ^0 j7 Q( Z% z4 y% r9 B* [- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options. N6 G D: K4 o y% K: e3 ]2 C
- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers. # Y$ Y( h( ?( T* L2 ]2 C
- Removed all TIGs in UCF. The reset signal is now registered in every module.
A X8 `; I2 t, f- k. l% y- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
8 \3 g, b4 |" ~: L9 [9 c& S- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
" c2 I, ]5 G6 t3 p4 Z- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
, n# V, Z+ `. V( e' j- Replaced `defines with localparams for Verilog. 4 J4 i' u4 G) B7 c
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. " l+ Q5 l; P- X. d: v& C7 k# b
- Several state machines now use "One-Hot Encoding". ' C3 ^+ d# N2 b/ W9 m0 a
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
0 u, W7 O/ }/ e4 j6 k+ f X- Signal INIT_DONE is brought to top module. 9 d& e U8 p1 ?$ W& O
- Removed the UniSim primitive components declaration from VHDL modules. ; a8 v/ |$ E0 L: U4 N4 O: O, N
- We now support all multiples of 8-bit data widths even for x16 memory devices. # Q$ ]: o2 u4 K% E
- We support memory devices of speed grades -3 and -667. ! Z( u6 ^" u: m
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
5 r, w7 w) q% Q" qa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
s$ ], o" s0 [1 ?0 s) Cb. WASSO is applied to all the memory interface signals. ! H7 V9 r# o$ n' L
c. Signals such as "Error" outputs are not part of the WASSO count. , _! M% T0 L+ o5 n1 W- x
6 V3 B. [7 U! I, }% l& ^+ R9 @7 E
DDR2 SDRAM SERDES Clocking
/ o+ E* s6 R) O( O; s( r5 Z$ }8 t1 d- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note.
, `/ ?. G! W3 h* l# {" z, I- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. + m2 O8 [9 u( h3 p! i* \
- Support for ODT. 4 G" A7 k G1 v( d* \, ]- f3 t
- DQS# Enable is selectable from GUI through Mode registers.
. }7 G/ B: @+ Y& P! _; n- Removed all TIGs in UCF. The reset signal is now registered in every module.
* Y) J) }. ?/ S/ a+ E- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. + v: C% e2 D% {: ^: ?
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
( H/ `( y B* C" i$ ]- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
! ]7 R: {( \, _7 L- Replaced `defines with localparams for Verilog. ' b7 U7 J5 I" f) G
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
( t- T* ?8 J2 d0 F( \/ t- Removed the UniSim primitive components declaration from VHDL modules. 7 U% n3 ~2 r- E& ~- f: [# F
- We now support all multiples of 8-bit data widths even for x16 memory devices. 5 ~% ]* V# C, G$ }3 @3 Y
- Signal INIT_COMPLETE is brought to top module.
. \( d' [8 w, g; v- Memory devices of speed grades -5E and -40E are now supported. 3 S5 Y* _' Y5 u# p$ R/ A
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. / s$ p$ g& R& _, F* n
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
6 y& O7 ?7 I- r0 O. H- |b. WASSO is applied to all the memory interface signals. / U# A& H3 D1 o
c. Signals such as "Error" outputs are not part of the WASSO count. ) X3 ?% R3 O+ ?. Z* n5 I$ e _3 Q2 B1 B
0 B) B/ ]$ W$ {, h, aDDR SDRAM * |+ o+ r" U/ z9 ], s
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
1 `! o P% z3 J7 i; {: I- Removed all TIGs in UCF. The reset signal is now registered in every module.
$ R8 n1 A( u: W1 e! C" O) g, F- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. & I1 F/ u$ J u4 `& L. v, t
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
/ u, T; f Z3 U3 W5 {# I9 {- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 1 T8 P0 Z& z" T, R: \- {
- Replaced `defines with localparams for Verilog.
6 O& @) w, L8 u6 W+ c+ N" C- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. 4 l. B) Q% h6 i% R; _$ _( I+ _
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. |5 g+ m0 r: s& ]5 i, e
- Removed the UniSim primitive components declaration from VHDL modules. 6 I1 ^3 e+ [* E, A% C! R2 J
- We now support all multiples of 8-bit data widths even for x16 memory devices. 5 N. W+ P/ d5 Z( l% ^! `4 b
- The signal "init_done" is now a port in the top module.
; x2 n, g; p i2 Z6 c4 B- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
3 I* {2 S8 N" S) ` \# f( V* da. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. " K2 @# S3 r6 y( v- d" P+ `- j
b. WASSO is applied to all the memory interface signals.
: ~! d% Z, ~! u5 v, h* c% Qc. Signals such as "Error" outputs are not part of the WASSO count. 9 l8 U- G8 I9 ^* A* n$ L4 e9 J
2 q" V# Q* q9 u. ?- ^7 PRLDRAM II
) T. k! B/ o, i5 O+ |- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. ( s& X- B2 H2 F$ d6 O7 S, D, m
- Removed all TIGs in UCF. The reset signal is now registered in every module.
8 j$ i5 l$ b; F q* N- The design now uses CLK0, instead of CLK50 and div16clk. 0 H% |/ k! d8 |
- CLK200 is changed to differential clocks in mem_interface_top module (Design top).
6 a# b+ n6 G2 h- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal. P, n1 \4 f- \- D" c U
- Removed unused parameters from the parameter file.
* j: u0 {/ N: N! c, Q, L4 K- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
; N2 S& U4 O- J K: {8 m- Replaced `defines with localparams for Verilog.
0 p& [& m- K3 a- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 5 p: H! \, F$ Y) |: D0 K4 O
- Removed the UniSim primitive components declaration from VHDL modules.
% c1 f* g$ ^4 d- The signal "INIT_DONE" is now a port in the top module. 2 U; i- j6 x8 G
- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8.
, }1 R5 ]( @1 G) K6 ]4 G/ _- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets.
$ c- `* j! w$ [7 z% K, Q2 h- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
. v1 \$ n) p9 M- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. % v5 T: g! M" I6 I5 B& r) k
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. , p3 }: f* i. f% V% y. ?
b. WASSO count is applied on output signals only for SIO memory types.
; u$ y7 `; v# Q+ T+ f# J% qc. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool. 7 v5 v# t5 m( s& |4 ^6 [9 n
( b3 ?/ O* `3 N- e( B& q2 b
QDRII SRAM A* F9 U1 w7 E9 o9 h( O
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
0 k9 U; N5 ]2 I/ ^$ F* E- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic. 8 G* A; M7 e/ C' d9 l
- Supports generation of designs with out DCM. # S5 R1 v( J( Y3 o+ p6 A+ h
- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC.
0 u1 N2 c& |5 o- _- Removed all TIGs in UCF. The reset signal is now registered in every module. $ i0 U! W/ i4 V- i
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
: v- [: n" a; ~/ T0 k; Z0 E- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. $ C/ M) q1 ^# T) ~
- Replaced `defines with localparams for Verilog. / F+ L" d M. O1 e( c- q! y
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 4 Y# z' c0 T) K% o! }" M: P% C
- Removed the UniSim primitive components declaration from VHDL modules.
) G3 r- ` h9 G- The signal "DLY_CAL_DONE" is now a port in the top module.
% y0 D# L5 q4 o$ V8 M( C9 n- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. - X9 R/ C% o: R& [7 F
- Added support for DDR Byte writes.
1 ?; P2 A* @" Q" N3 o, ^7 k# A- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
; B! [) t/ q; R% _( n- ja. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
. }, S& c1 E- d3 Z8 x9 }6 l) z8 Rb. WASSO is applied to the output signals only. ( ^0 T7 m e, R& d
c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool. ; }+ P% H9 g: @: p2 a' A1 S
: K& j1 Q+ j& e7 r( g. y
DDRII SRAM
1 E+ [7 m6 T8 @% G1 \$ w. \0 R- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 7 O7 t) L" g% A/ x: [0 }- u
- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic.
# k0 v* i) \' w) f% j# Q- Supports generation of designs with out DCM.
% c/ r! P: }4 Q1 x9 L c$ W0 Z2 c- Part CY7C1526V18-250BZC has been removed from Memory Parts list. ?' G$ X3 y: I+ ?2 X8 K" J5 v; `
- Removed all TIGs in UCF. The reset signal is now registered in every module. 9 t4 ]6 y) \% _$ i/ N* A
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 7 }8 s5 o: G: K( Y! r
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
5 m; b5 X4 _: w9 X2 G# X' @2 R- S- Replaced `defines with localparams for Verilog. 2 ^# ]# [% R. E9 w: e
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
$ }& V( M% p" M- Removed the UniSim primitive components declaration from VHDL modules.
' ]7 _9 N# u r4 y R( H6 P5 O6 ]6 T- The signal "DLY_CAL_DONE" is now a port in the top module.
0 k7 X" t* G4 @" C- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
2 i' S, C6 V1 N' F% ~2 L- Added support for DDR Byte writes. # ]# B) c8 b0 Z1 w/ v/ ^3 t
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. + {8 Q9 z" L# l5 E9 _
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
- {. ~8 \% n& q* ^# U9 K7 M" db. WASSO is applied to all the memory interface signals.
9 y/ @& u5 o4 r: B& y/ rc. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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