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回復 #1 option318 的帖子
回復 #1 option318 的帖子
: P9 T6 }4 ^1 n: R" R( t(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一% y. x7 z2 _. q) M/ c! K" f: c
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
$ X' W8 m2 {1 W+ q K pll ,且亦有unstability issue
- n( u# J; P" H+ j0 ~0 F: Y(see Charge-pump phase lock loops paper by Gardner
$ D! p* H# z5 [- |IEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980); m- a, f R, [
(2) loop BW is related to jitter (or phase noise) ,and locking time J6 c9 [: K0 y+ O4 Z
so you have to consider loop BW from jitter & locking time spec9 o3 i8 ?4 N- m; ]) b
(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq4 [" i% A8 E, _3 g" b6 N: o
(4) In my opinion ,gain margin is not considered in pll design |
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